108 lines
3.4 KiB
C
108 lines
3.4 KiB
C
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/acr.h>
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#include <nvfw/flcn.h>
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#include <nvfw/pmu.h>
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static int
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gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv,
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struct nvfw_falcon_msg *hdr)
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{
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struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg =
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container_of(hdr, typeof(*msg), msg.hdr);
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return msg->falcon_mask;
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}
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static int
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gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon *falcon, u32 mask)
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{
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struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
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struct nv_pmu_acr_bootstrap_multiple_falcons_cmd cmd = {
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.cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
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.cmd.hdr.size = sizeof(cmd),
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.cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS,
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.flags = NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES,
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.falcon_mask = mask,
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.wpr_lo = 0, /*XXX*/
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.wpr_hi = 0, /*XXX*/
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};
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int ret;
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ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
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gp10b_pmu_acr_bootstrap_multiple_falcons_cb,
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&pmu->subdev, msecs_to_jiffies(1000));
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if (ret >= 0) {
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if (ret != cmd.falcon_mask)
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ret = -EIO;
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else
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ret = 0;
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}
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return ret;
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}
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static const struct nvkm_acr_lsf_func
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gp10b_pmu_acr = {
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.flags = NVKM_ACR_LSF_DMACTL_REQ_CTX,
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.bld_size = sizeof(struct loader_config),
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.bld_write = gm20b_pmu_acr_bld_write,
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.bld_patch = gm20b_pmu_acr_bld_patch,
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.boot = gm20b_pmu_acr_boot,
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.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) |
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BIT_ULL(NVKM_ACR_LSF_FECS) |
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BIT_ULL(NVKM_ACR_LSF_GPCCS),
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.bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon,
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.bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons,
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};
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static const struct nvkm_pmu_func
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gp10b_pmu = {
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.flcn = &gm200_pmu_flcn,
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.enabled = gf100_pmu_enabled,
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.intr = gt215_pmu_intr,
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.recv = gm20b_pmu_recv,
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.initmsg = gm20b_pmu_initmsg,
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.reset = gp102_pmu_reset,
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
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MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
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MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
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#endif
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static const struct nvkm_pmu_fwif
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gp10b_pmu_fwif[] = {
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{ 0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr },
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{ -1, gm200_pmu_nofw, &gp10b_pmu },
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{}
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};
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int
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gp10b_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_pmu **ppmu)
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{
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return nvkm_pmu_new_(gp10b_pmu_fwif, device, type, inst, ppmu);
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}
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