488 lines
13 KiB
C
488 lines
13 KiB
C
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/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/falcon.h>
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#include <core/firmware.h>
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#include <core/memory.h>
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#include <subdev/mc.h>
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#include <subdev/mmu.h>
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#include <subdev/pmu.h>
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#include <subdev/timer.h>
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#include <nvfw/acr.h>
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#include <nvfw/flcn.h>
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const struct nvkm_acr_func
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gm200_acr = {
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};
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int
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gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
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{
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nvkm_warn(&acr->subdev, "firmware unavailable\n");
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return 0;
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}
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int
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gm200_acr_init(struct nvkm_acr *acr)
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{
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return nvkm_acr_hsf_boot(acr, "load");
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}
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void
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gm200_acr_wpr_check(struct nvkm_acr *acr, u64 *start, u64 *limit)
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{
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struct nvkm_device *device = acr->subdev.device;
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nvkm_wr32(device, 0x100cd4, 2);
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*start = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
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nvkm_wr32(device, 0x100cd4, 3);
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*limit = (u64)(nvkm_rd32(device, 0x100cd4) & 0xffffff00) << 8;
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*limit = *limit + 0x20000;
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}
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void
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gm200_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
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{
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struct nvkm_subdev *subdev = &acr->subdev;
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struct wpr_header hdr;
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struct lsb_header lsb;
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struct nvkm_acr_lsf *lsfw;
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u32 offset = 0;
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do {
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nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
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wpr_header_dump(subdev, &hdr);
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list_for_each_entry(lsfw, &acr->lsfw, head) {
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if (lsfw->id != hdr.falcon_id)
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continue;
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nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
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lsb_header_dump(subdev, &lsb);
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lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
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break;
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}
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offset += sizeof(hdr);
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} while (hdr.falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID);
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}
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void
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gm200_acr_wpr_build_lsb_tail(struct nvkm_acr_lsfw *lsfw,
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struct lsb_header_tail *hdr)
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{
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hdr->ucode_off = lsfw->offset.img;
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hdr->ucode_size = lsfw->ucode_size;
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hdr->data_size = lsfw->data_size;
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hdr->bl_code_size = lsfw->bootloader_size;
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hdr->bl_imem_off = lsfw->bootloader_imem_offset;
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hdr->bl_data_off = lsfw->offset.bld;
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hdr->bl_data_size = lsfw->bl_data_size;
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hdr->app_code_off = lsfw->app_start_offset +
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lsfw->app_resident_code_offset;
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hdr->app_code_size = lsfw->app_resident_code_size;
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hdr->app_data_off = lsfw->app_start_offset +
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lsfw->app_resident_data_offset;
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hdr->app_data_size = lsfw->app_resident_data_size;
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hdr->flags = lsfw->func->flags;
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}
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static int
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gm200_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
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{
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struct lsb_header hdr;
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if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
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return -EINVAL;
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memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
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gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
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nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
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return 0;
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}
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int
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gm200_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
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{
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struct nvkm_acr_lsfw *lsfw;
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u32 offset = 0;
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int ret;
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/* Fill per-LSF structures. */
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list_for_each_entry(lsfw, &acr->lsfw, head) {
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struct wpr_header hdr = {
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.falcon_id = lsfw->id,
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.lsb_offset = lsfw->offset.lsb,
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.bootstrap_owner = NVKM_ACR_LSF_PMU,
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.lazy_bootstrap = rtos && lsfw->id != rtos->id,
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.status = WPR_HEADER_V0_STATUS_COPY,
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};
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/* Write WPR header. */
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nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
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offset += sizeof(hdr);
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/* Write LSB header. */
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ret = gm200_acr_wpr_build_lsb(acr, lsfw);
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if (ret)
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return ret;
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/* Write ucode image. */
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nvkm_wobj(acr->wpr, lsfw->offset.img,
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lsfw->img.data,
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lsfw->img.size);
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/* Write bootloader data. */
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lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
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}
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/* Finalise WPR. */
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nvkm_wo32(acr->wpr, offset, WPR_HEADER_V0_FALCON_ID_INVALID);
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return 0;
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}
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static int
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gm200_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
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{
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int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
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ALIGN(wpr_size, 0x40000), 0x40000, true,
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&acr->wpr);
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if (ret)
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return ret;
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acr->wpr_start = nvkm_memory_addr(acr->wpr);
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acr->wpr_end = acr->wpr_start + nvkm_memory_size(acr->wpr);
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return 0;
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}
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u32
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gm200_acr_wpr_layout(struct nvkm_acr *acr)
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{
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struct nvkm_acr_lsfw *lsfw;
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u32 wpr = 0;
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wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header);
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list_for_each_entry(lsfw, &acr->lsfw, head) {
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wpr = ALIGN(wpr, 256);
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lsfw->offset.lsb = wpr;
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wpr += sizeof(struct lsb_header);
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wpr = ALIGN(wpr, 4096);
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lsfw->offset.img = wpr;
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wpr += lsfw->img.size;
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wpr = ALIGN(wpr, 256);
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lsfw->offset.bld = wpr;
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lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
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wpr += lsfw->bl_data_size;
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}
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return wpr;
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}
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int
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gm200_acr_wpr_parse(struct nvkm_acr *acr)
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{
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const struct wpr_header *hdr = (void *)acr->wpr_fw->data;
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struct nvkm_acr_lsfw *lsfw;
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while (hdr->falcon_id != WPR_HEADER_V0_FALCON_ID_INVALID) {
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wpr_header_dump(&acr->subdev, hdr);
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lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id);
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if (IS_ERR(lsfw))
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return PTR_ERR(lsfw);
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}
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return 0;
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}
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void
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gm200_acr_hsfw_bld(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
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{
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struct flcn_bl_dmem_desc_v1 hsdesc = {
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.ctx_dma = FALCON_DMAIDX_VIRT,
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.code_dma_base = hsf->vma->addr,
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.non_sec_code_off = hsf->non_sec_addr,
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.non_sec_code_size = hsf->non_sec_size,
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.sec_code_off = hsf->sec_addr,
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.sec_code_size = hsf->sec_size,
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.code_entry_point = 0,
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.data_dma_base = hsf->vma->addr + hsf->data_addr,
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.data_size = hsf->data_size,
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};
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flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hsdesc);
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nvkm_falcon_load_dmem(hsf->falcon, &hsdesc, 0, sizeof(hsdesc), 0);
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}
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int
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gm200_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf,
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u32 intr_clear, u32 mbox0_ok)
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{
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struct nvkm_subdev *subdev = &acr->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_falcon *falcon = hsf->falcon;
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u32 mbox0, mbox1;
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int ret;
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/* Reset falcon. */
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nvkm_falcon_reset(falcon);
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nvkm_falcon_bind_context(falcon, acr->inst);
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/* Load bootloader into IMEM. */
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nvkm_falcon_load_imem(falcon, hsf->imem,
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falcon->code.limit - hsf->imem_size,
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hsf->imem_size,
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hsf->imem_tag,
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0, false);
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/* Load bootloader data into DMEM. */
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hsf->func->bld(acr, hsf);
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/* Boot the falcon. */
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nvkm_mc_intr_mask(device, falcon->owner->type, falcon->owner->inst, false);
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nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5);
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nvkm_falcon_set_start_addr(falcon, hsf->imem_tag << 8);
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nvkm_falcon_start(falcon);
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ret = nvkm_falcon_wait_for_halt(falcon, 100);
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if (ret)
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return ret;
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/* Check for successful completion. */
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mbox0 = nvkm_falcon_rd32(falcon, 0x040);
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mbox1 = nvkm_falcon_rd32(falcon, 0x044);
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nvkm_debug(subdev, "mailbox %08x %08x\n", mbox0, mbox1);
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if (mbox0 && mbox0 != mbox0_ok)
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return -EIO;
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nvkm_falcon_clear_interrupt(falcon, intr_clear);
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nvkm_mc_intr_mask(device, falcon->owner->type, falcon->owner->inst, true);
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return ret;
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}
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int
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gm200_acr_hsfw_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw,
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struct nvkm_falcon *falcon)
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{
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struct nvkm_subdev *subdev = &acr->subdev;
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struct nvkm_acr_hsf *hsf;
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int ret;
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/* Patch the appropriate signature (production/debug) into the FW
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* image, as determined by the mode the falcon is in.
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*/
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ret = nvkm_falcon_get(falcon, subdev);
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if (ret)
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return ret;
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if (hsfw->sig.patch_loc) {
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if (!falcon->debug) {
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nvkm_debug(subdev, "patching production signature\n");
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memcpy(hsfw->image + hsfw->sig.patch_loc,
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hsfw->sig.prod.data,
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hsfw->sig.prod.size);
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} else {
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nvkm_debug(subdev, "patching debug signature\n");
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memcpy(hsfw->image + hsfw->sig.patch_loc,
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hsfw->sig.dbg.data,
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hsfw->sig.dbg.size);
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}
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}
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nvkm_falcon_put(falcon, subdev);
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if (!(hsf = kzalloc(sizeof(*hsf), GFP_KERNEL)))
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return -ENOMEM;
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hsf->func = hsfw->func;
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hsf->name = hsfw->name;
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list_add_tail(&hsf->head, &acr->hsf);
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hsf->imem_size = hsfw->imem_size;
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hsf->imem_tag = hsfw->imem_tag;
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hsf->imem = kmemdup(hsfw->imem, hsfw->imem_size, GFP_KERNEL);
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if (!hsf->imem)
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return -ENOMEM;
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hsf->non_sec_addr = hsfw->non_sec_addr;
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hsf->non_sec_size = hsfw->non_sec_size;
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hsf->sec_addr = hsfw->sec_addr;
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hsf->sec_size = hsfw->sec_size;
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hsf->data_addr = hsfw->data_addr;
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hsf->data_size = hsfw->data_size;
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/* Make the FW image accessible to the HS bootloader. */
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ret = nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST,
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hsfw->image_size, 0x1000, false, &hsf->ucode);
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if (ret)
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return ret;
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|
|
|
||
|
|
nvkm_kmap(hsf->ucode);
|
||
|
|
nvkm_wobj(hsf->ucode, 0, hsfw->image, hsfw->image_size);
|
||
|
|
nvkm_done(hsf->ucode);
|
||
|
|
|
||
|
|
ret = nvkm_vmm_get(acr->vmm, 12, nvkm_memory_size(hsf->ucode),
|
||
|
|
&hsf->vma);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = nvkm_memory_map(hsf->ucode, 0, acr->vmm, hsf->vma, NULL, 0);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
hsf->falcon = falcon;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
gm200_acr_unload_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
|
||
|
|
{
|
||
|
|
return gm200_acr_hsfw_boot(acr, hsf, 0, 0x1d);
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
gm200_acr_unload_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
|
||
|
|
{
|
||
|
|
return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct nvkm_acr_hsf_func
|
||
|
|
gm200_acr_unload_0 = {
|
||
|
|
.load = gm200_acr_unload_load,
|
||
|
|
.boot = gm200_acr_unload_boot,
|
||
|
|
.bld = gm200_acr_hsfw_bld,
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gm204/acr/ucode_unload.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gm206/acr/ucode_unload.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp100/acr/ucode_unload.bin");
|
||
|
|
|
||
|
|
static const struct nvkm_acr_hsf_fwif
|
||
|
|
gm200_acr_unload_fwif[] = {
|
||
|
|
{ 0, nvkm_acr_hsfw_load, &gm200_acr_unload_0 },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
gm200_acr_load_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf)
|
||
|
|
{
|
||
|
|
return gm200_acr_hsfw_boot(acr, hsf, 0x10, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
gm200_acr_load_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw)
|
||
|
|
{
|
||
|
|
struct flcn_acr_desc *desc = (void *)&hsfw->image[hsfw->data_addr];
|
||
|
|
|
||
|
|
desc->wpr_region_id = 1;
|
||
|
|
desc->regions.no_regions = 2;
|
||
|
|
desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
|
||
|
|
desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
|
||
|
|
desc->regions.region_props[0].region_id = 1;
|
||
|
|
desc->regions.region_props[0].read_mask = 0xf;
|
||
|
|
desc->regions.region_props[0].write_mask = 0xc;
|
||
|
|
desc->regions.region_props[0].client_mask = 0x2;
|
||
|
|
flcn_acr_desc_dump(&acr->subdev, desc);
|
||
|
|
|
||
|
|
return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->pmu->falcon);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_acr_hsf_func
|
||
|
|
gm200_acr_load_0 = {
|
||
|
|
.load = gm200_acr_load_load,
|
||
|
|
.boot = gm200_acr_load_boot,
|
||
|
|
.bld = gm200_acr_hsfw_bld,
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin");
|
||
|
|
|
||
|
|
MODULE_FIRMWARE("nvidia/gm204/acr/bl.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gm204/acr/ucode_load.bin");
|
||
|
|
|
||
|
|
MODULE_FIRMWARE("nvidia/gm206/acr/bl.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gm206/acr/ucode_load.bin");
|
||
|
|
|
||
|
|
MODULE_FIRMWARE("nvidia/gp100/acr/bl.bin");
|
||
|
|
MODULE_FIRMWARE("nvidia/gp100/acr/ucode_load.bin");
|
||
|
|
|
||
|
|
static const struct nvkm_acr_hsf_fwif
|
||
|
|
gm200_acr_load_fwif[] = {
|
||
|
|
{ 0, nvkm_acr_hsfw_load, &gm200_acr_load_0 },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct nvkm_acr_func
|
||
|
|
gm200_acr_0 = {
|
||
|
|
.load = gm200_acr_load_fwif,
|
||
|
|
.unload = gm200_acr_unload_fwif,
|
||
|
|
.wpr_parse = gm200_acr_wpr_parse,
|
||
|
|
.wpr_layout = gm200_acr_wpr_layout,
|
||
|
|
.wpr_alloc = gm200_acr_wpr_alloc,
|
||
|
|
.wpr_build = gm200_acr_wpr_build,
|
||
|
|
.wpr_patch = gm200_acr_wpr_patch,
|
||
|
|
.wpr_check = gm200_acr_wpr_check,
|
||
|
|
.init = gm200_acr_init,
|
||
|
|
.bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) |
|
||
|
|
BIT_ULL(NVKM_ACR_LSF_GPCCS),
|
||
|
|
};
|
||
|
|
|
||
|
|
static int
|
||
|
|
gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
|
||
|
|
{
|
||
|
|
struct nvkm_subdev *subdev = &acr->subdev;
|
||
|
|
const struct nvkm_acr_hsf_fwif *hsfwif;
|
||
|
|
|
||
|
|
hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
|
||
|
|
acr, "acr/bl", "acr/ucode_load", "load");
|
||
|
|
if (IS_ERR(hsfwif))
|
||
|
|
return PTR_ERR(hsfwif);
|
||
|
|
|
||
|
|
hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
|
||
|
|
acr, "acr/bl", "acr/ucode_unload",
|
||
|
|
"unload");
|
||
|
|
if (IS_ERR(hsfwif))
|
||
|
|
return PTR_ERR(hsfwif);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_acr_fwif
|
||
|
|
gm200_acr_fwif[] = {
|
||
|
|
{ 0, gm200_acr_load, &gm200_acr_0 },
|
||
|
|
{ -1, gm200_acr_nofw, &gm200_acr },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
gm200_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||
|
|
struct nvkm_acr **pacr)
|
||
|
|
{
|
||
|
|
return nvkm_acr_new_(gm200_acr_fwif, device, type, inst, pacr);
|
||
|
|
}
|