205 lines
7.4 KiB
C
205 lines
7.4 KiB
C
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/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <nvif/class.h>
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static void
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tu102_gr_init_fecs_exceptions(struct gf100_gr *gr)
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{
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nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002);
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}
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static void
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tu102_gr_init_fs(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int sm;
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gp100_grctx_generate_smid_config(gr);
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gk104_grctx_generate_gpc_tpc_nr(gr);
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for (sm = 0; sm < gr->sm_nr; sm++) {
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nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 +
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gr->sm[sm].tpc * 4), sm);
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}
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gm200_grctx_generate_dist_skip_table(gr);
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gf100_gr_init_num_tpc_per_gpc(gr, true, true);
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}
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static void
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tu102_gr_init_zcull(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
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const u8 tile_nr = ALIGN(gr->tpc_total, 64);
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u8 bank[GPC_MAX] = {}, gpc, i, j;
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u32 data;
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for (i = 0; i < tile_nr; i += 8) {
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for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
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data |= bank[gr->tile[i + j]] << (j * 4);
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bank[gr->tile[i + j]]++;
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}
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nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
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}
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
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gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
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gr->tpc_total);
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nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
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}
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nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
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}
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static void
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tu102_gr_init_gpc_mmu(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);
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nvkm_wr32(device, 0x418890, 0x00000000);
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nvkm_wr32(device, 0x418894, 0x00000000);
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nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
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nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
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nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
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}
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static const struct gf100_gr_func
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tu102_gr = {
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gm200_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_419bd8 = gv100_gr_init_419bd8,
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.init_gpc_mmu = tu102_gr_init_gpc_mmu,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = tu102_gr_init_zcull,
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.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
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.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
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.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
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.init_fs = tu102_gr_init_fs,
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.init_fecs_exceptions = tu102_gr_init_fecs_exceptions,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_504430 = gv100_gr_init_504430,
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.init_shader_exceptions = gv100_gr_init_shader_exceptions,
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.trap_mp = gv100_gr_trap_mp,
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.rops = gm200_gr_rops,
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.gpc_nr = 6,
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.tpc_nr = 5,
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.ppc_nr = 3,
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.grctx = &tu102_grctx,
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.zbc = &gp102_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, TURING_A, &gf100_fermi },
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{ -1, -1, TURING_COMPUTE_A },
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{}
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}
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};
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MODULE_FIRMWARE("nvidia/tu102/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu102/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu104/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu106/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu117/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin");
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static const struct gf100_gr_fwif
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tu102_gr_fwif[] = {
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{ 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr },
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{ -1, gm200_gr_nofw },
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{}
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};
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int
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tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr);
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}
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