309 lines
9.0 KiB
C
309 lines
9.0 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "changf100.h"
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#include <core/client.h>
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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#include <nvif/cl906f.h>
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#include <nvif/unpack.h>
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int
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gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
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struct nvkm_event **pevent)
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{
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switch (type) {
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case NV906F_V0_NTFY_NON_STALL_INTERRUPT:
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*pevent = &chan->fifo->uevent;
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return 0;
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case NV906F_V0_NTFY_KILLED:
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*pevent = &chan->fifo->kevent;
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return 0;
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default:
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break;
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}
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return -EINVAL;
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}
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static u32
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gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
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{
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switch (engine->subdev.type) {
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case NVKM_ENGINE_SW : return 0;
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case NVKM_ENGINE_GR : return 0x0210;
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case NVKM_ENGINE_CE : return 0x0230 + (engine->subdev.inst * 0x10);
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case NVKM_ENGINE_MSPDEC: return 0x0250;
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case NVKM_ENGINE_MSPPP : return 0x0260;
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case NVKM_ENGINE_MSVLD : return 0x0270;
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default:
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WARN_ON(1);
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return 0;
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}
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}
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static struct gf100_fifo_engn *
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gf100_fifo_gpfifo_engine(struct gf100_fifo_chan *chan, struct nvkm_engine *engine)
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{
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int engi = chan->base.fifo->func->engine_id(chan->base.fifo, engine);
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if (engi >= 0)
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return &chan->engn[engi];
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return NULL;
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}
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static int
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gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine, bool suspend)
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{
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const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
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struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
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struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_gpuobj *inst = chan->base.inst;
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int ret = 0;
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mutex_lock(&chan->fifo->base.mutex);
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nvkm_wr32(device, 0x002634, chan->base.chid);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x002634) == chan->base.chid)
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break;
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) < 0) {
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nvkm_error(subdev, "channel %d [%s] kick timeout\n",
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chan->base.chid, chan->base.object.client->name);
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ret = -ETIMEDOUT;
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}
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mutex_unlock(&chan->fifo->base.mutex);
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if (ret && suspend)
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return ret;
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if (offset) {
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nvkm_kmap(inst);
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nvkm_wo32(inst, offset + 0x00, 0x00000000);
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nvkm_wo32(inst, offset + 0x04, 0x00000000);
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nvkm_done(inst);
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}
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return ret;
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}
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static int
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gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine)
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{
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const u32 offset = gf100_fifo_gpfifo_engine_addr(engine);
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struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
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struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine);
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struct nvkm_gpuobj *inst = chan->base.inst;
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if (offset) {
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nvkm_kmap(inst);
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nvkm_wo32(inst, offset + 0x00, lower_32_bits(engn->vma->addr) | 4);
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nvkm_wo32(inst, offset + 0x04, upper_32_bits(engn->vma->addr));
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nvkm_done(inst);
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}
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return 0;
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}
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static void
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gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine)
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{
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struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
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struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine);
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nvkm_vmm_put(chan->base.vmm, &engn->vma);
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nvkm_gpuobj_del(&engn->inst);
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}
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static int
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gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine,
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struct nvkm_object *object)
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{
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struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
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struct gf100_fifo_engn *engn = gf100_fifo_gpfifo_engine(chan, engine);
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int ret;
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if (!gf100_fifo_gpfifo_engine_addr(engine))
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return 0;
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ret = nvkm_object_bind(object, NULL, 0, &engn->inst);
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if (ret)
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return ret;
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ret = nvkm_vmm_get(chan->base.vmm, 12, engn->inst->size, &engn->vma);
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if (ret)
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return ret;
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return nvkm_memory_map(engn->inst, 0, chan->base.vmm, engn->vma, NULL, 0);
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}
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static void
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gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
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{
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struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
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struct gf100_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 coff = chan->base.chid * 8;
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if (!list_empty(&chan->head) && !chan->killed) {
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gf100_fifo_runlist_remove(fifo, chan);
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nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000);
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gf100_fifo_runlist_commit(fifo);
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}
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gf100_fifo_intr_engine(fifo);
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nvkm_wr32(device, 0x003000 + coff, 0x00000000);
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}
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static void
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gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
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{
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struct gf100_fifo_chan *chan = gf100_fifo_chan(base);
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struct gf100_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 addr = chan->base.inst->addr >> 12;
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u32 coff = chan->base.chid * 8;
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nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr);
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if (list_empty(&chan->head) && !chan->killed) {
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gf100_fifo_runlist_insert(fifo, chan);
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nvkm_wr32(device, 0x003004 + coff, 0x001f0001);
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gf100_fifo_runlist_commit(fifo);
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}
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}
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static void *
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gf100_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
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{
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return gf100_fifo_chan(base);
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}
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static const struct nvkm_fifo_chan_func
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gf100_fifo_gpfifo_func = {
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.dtor = gf100_fifo_gpfifo_dtor,
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.init = gf100_fifo_gpfifo_init,
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.fini = gf100_fifo_gpfifo_fini,
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.ntfy = gf100_fifo_chan_ntfy,
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.engine_ctor = gf100_fifo_gpfifo_engine_ctor,
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.engine_dtor = gf100_fifo_gpfifo_engine_dtor,
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.engine_init = gf100_fifo_gpfifo_engine_init,
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.engine_fini = gf100_fifo_gpfifo_engine_fini,
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};
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static int
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gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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union {
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struct fermi_channel_gpfifo_v0 v0;
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} *args = data;
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struct gf100_fifo *fifo = gf100_fifo(base);
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struct nvkm_object *parent = oclass->parent;
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struct gf100_fifo_chan *chan;
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u64 usermem, ioffset, ilength;
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int ret = -ENOSYS, i;
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nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
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"ioffset %016llx ilength %08x\n",
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args->v0.version, args->v0.vmm, args->v0.ioffset,
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args->v0.ilength);
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if (!args->v0.vmm)
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return -EINVAL;
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} else
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return ret;
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/* allocate channel */
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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*pobject = &chan->base.object;
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chan->fifo = fifo;
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INIT_LIST_HEAD(&chan->head);
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ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base,
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0x1000, 0x1000, true, args->v0.vmm, 0,
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BIT(GF100_FIFO_ENGN_GR) |
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BIT(GF100_FIFO_ENGN_MSPDEC) |
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BIT(GF100_FIFO_ENGN_MSPPP) |
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BIT(GF100_FIFO_ENGN_MSVLD) |
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BIT(GF100_FIFO_ENGN_CE0) |
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BIT(GF100_FIFO_ENGN_CE1) |
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BIT(GF100_FIFO_ENGN_SW),
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1, fifo->user.bar->addr, 0x1000,
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oclass, &chan->base);
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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/* clear channel control registers */
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usermem = chan->base.chid * 0x1000;
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ioffset = args->v0.ioffset;
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ilength = order_base_2(args->v0.ilength / 8);
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nvkm_kmap(fifo->user.mem);
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for (i = 0; i < 0x1000; i += 4)
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nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
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nvkm_done(fifo->user.mem);
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usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
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/* RAMFC */
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nvkm_kmap(chan->base.inst);
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nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
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nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
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nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
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nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
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nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
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nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
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(ilength << 16));
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nvkm_wo32(chan->base.inst, 0x54, 0x00000002);
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nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
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nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
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nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
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nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f);
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nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f);
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nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
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nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
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nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
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nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
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nvkm_done(chan->base.inst);
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return 0;
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}
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const struct nvkm_fifo_chan_oclass
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gf100_fifo_gpfifo_oclass = {
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.base.oclass = FERMI_CHANNEL_GPFIFO,
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.base.minver = 0,
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.base.maxver = 0,
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.ctor = gf100_fifo_gpfifo_new,
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};
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