227 lines
7.1 KiB
C
227 lines
7.1 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "channv04.h"
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#include "regsnv04.h"
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#include <core/client.h>
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#include <core/ramht.h>
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#include <subdev/instmem.h>
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#include <nvif/class.h>
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#include <nvif/cl006b.h>
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#include <nvif/unpack.h>
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void
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nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie)
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{
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struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
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struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
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mutex_lock(&chan->fifo->base.mutex);
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nvkm_ramht_remove(imem->ramht, cookie);
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mutex_unlock(&chan->fifo->base.mutex);
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}
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static int
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nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
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struct nvkm_object *object)
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{
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struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
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struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem;
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u32 context = 0x80000000 | chan->base.chid << 24;
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u32 handle = object->handle;
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int hash;
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switch (object->engine->subdev.type) {
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case NVKM_ENGINE_DMAOBJ:
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case NVKM_ENGINE_SW : context |= 0x00000000; break;
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case NVKM_ENGINE_GR : context |= 0x00010000; break;
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case NVKM_ENGINE_MPEG : context |= 0x00020000; break;
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default:
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WARN_ON(1);
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return -EINVAL;
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}
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mutex_lock(&chan->fifo->base.mutex);
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hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4,
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handle, context);
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mutex_unlock(&chan->fifo->base.mutex);
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return hash;
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}
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void
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nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
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{
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struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
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struct nv04_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_memory *fctx = device->imem->ramfc;
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const struct nv04_fifo_ramfc *c;
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unsigned long flags;
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u32 mask = fifo->base.nr - 1;
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u32 data = chan->ramfc;
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u32 chid;
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/* prevent fifo context switches */
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spin_lock_irqsave(&fifo->base.lock, flags);
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nvkm_wr32(device, NV03_PFIFO_CACHES, 0);
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/* if this channel is active, replace it with a null context */
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chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask;
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if (chid == chan->base.chid) {
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nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
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nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
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c = fifo->ramfc;
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nvkm_kmap(fctx);
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do {
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u32 rm = ((1ULL << c->bits) - 1) << c->regs;
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u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
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u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs;
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u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm);
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nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
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} while ((++c)->bits);
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nvkm_done(fctx);
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c = fifo->ramfc;
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do {
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nvkm_wr32(device, c->regp, 0x00000000);
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} while ((++c)->bits);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask);
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nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
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nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
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}
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/* restore normal operation, after disabling dma mode */
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nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);
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nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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}
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void
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nv04_fifo_dma_init(struct nvkm_fifo_chan *base)
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{
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struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
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struct nv04_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 mask = 1 << chan->base.chid;
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unsigned long flags;
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spin_lock_irqsave(&fifo->base.lock, flags);
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nvkm_mask(device, NV04_PFIFO_MODE, mask, mask);
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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}
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void *
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nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
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{
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struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
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struct nv04_fifo *fifo = chan->fifo;
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struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
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const struct nv04_fifo_ramfc *c = fifo->ramfc;
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nvkm_kmap(imem->ramfc);
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do {
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nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000);
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} while ((++c)->bits);
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nvkm_done(imem->ramfc);
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return chan;
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}
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const struct nvkm_fifo_chan_func
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nv04_fifo_dma_func = {
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.dtor = nv04_fifo_dma_dtor,
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.init = nv04_fifo_dma_init,
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.fini = nv04_fifo_dma_fini,
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.object_ctor = nv04_fifo_dma_object_ctor,
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.object_dtor = nv04_fifo_dma_object_dtor,
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};
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static int
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nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
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void *data, u32 size, struct nvkm_object **pobject)
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{
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struct nvkm_object *parent = oclass->parent;
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union {
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struct nv03_channel_dma_v0 v0;
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} *args = data;
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struct nv04_fifo *fifo = nv04_fifo(base);
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struct nv04_fifo_chan *chan = NULL;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_instmem *imem = device->imem;
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int ret = -ENOSYS;
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nvif_ioctl(parent, "create channel dma size %d\n", size);
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if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
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nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx "
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"offset %08x\n", args->v0.version,
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args->v0.pushbuf, args->v0.offset);
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if (!args->v0.pushbuf)
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return -EINVAL;
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} else
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return ret;
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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*pobject = &chan->base.object;
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ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
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0x1000, 0x1000, false, 0, args->v0.pushbuf,
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BIT(NV04_FIFO_ENGN_SW) |
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BIT(NV04_FIFO_ENGN_GR) |
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BIT(NV04_FIFO_ENGN_DMA),
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0, 0x800000, 0x10000, oclass, &chan->base);
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chan->fifo = fifo;
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if (ret)
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return ret;
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args->v0.chid = chan->base.chid;
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chan->ramfc = chan->base.chid * 32;
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nvkm_kmap(imem->ramfc);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4);
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nvkm_wo32(imem->ramfc, chan->ramfc + 0x10,
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NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
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nvkm_done(imem->ramfc);
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return 0;
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}
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const struct nvkm_fifo_chan_oclass
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nv04_fifo_dma_oclass = {
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.base.oclass = NV03_CHANNEL_DMA,
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.base.minver = 0,
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.base.maxver = 0,
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.ctor = nv04_fifo_dma_new,
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};
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