68 lines
2.9 KiB
C
68 lines
2.9 KiB
C
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/* SPDX-License-Identifier: MIT */
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#ifndef __NVIF_CL0002_H__
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#define __NVIF_CL0002_H__
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struct nv_dma_v0 {
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__u8 version;
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#define NV_DMA_V0_TARGET_VM 0x00
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#define NV_DMA_V0_TARGET_VRAM 0x01
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#define NV_DMA_V0_TARGET_PCI 0x02
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#define NV_DMA_V0_TARGET_PCI_US 0x03
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#define NV_DMA_V0_TARGET_AGP 0x04
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__u8 target;
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#define NV_DMA_V0_ACCESS_VM 0x00
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#define NV_DMA_V0_ACCESS_RD 0x01
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#define NV_DMA_V0_ACCESS_WR 0x02
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#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
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__u8 access;
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__u8 pad03[5];
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__u64 start;
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__u64 limit;
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/* ... chipset-specific class data */
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};
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struct nv50_dma_v0 {
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__u8 version;
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#define NV50_DMA_V0_PRIV_VM 0x00
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#define NV50_DMA_V0_PRIV_US 0x01
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#define NV50_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define NV50_DMA_V0_PART_VM 0x00
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#define NV50_DMA_V0_PART_256 0x01
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#define NV50_DMA_V0_PART_1KB 0x02
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__u8 part;
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#define NV50_DMA_V0_COMP_NONE 0x00
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#define NV50_DMA_V0_COMP_1 0x01
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#define NV50_DMA_V0_COMP_2 0x02
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#define NV50_DMA_V0_COMP_VM 0x03
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__u8 comp;
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#define NV50_DMA_V0_KIND_PITCH 0x00
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#define NV50_DMA_V0_KIND_VM 0x7f
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__u8 kind;
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__u8 pad05[3];
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};
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struct gf100_dma_v0 {
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__u8 version;
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#define GF100_DMA_V0_PRIV_VM 0x00
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#define GF100_DMA_V0_PRIV_US 0x01
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#define GF100_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define GF100_DMA_V0_KIND_PITCH 0x00
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#define GF100_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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struct gf119_dma_v0 {
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__u8 version;
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#define GF119_DMA_V0_PAGE_LP 0x00
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#define GF119_DMA_V0_PAGE_SP 0x01
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__u8 page;
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#define GF119_DMA_V0_KIND_PITCH 0x00
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#define GF119_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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#endif
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