432 lines
14 KiB
C
432 lines
14 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_GFX_H__
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#define __AMDGPU_GFX_H__
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/*
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* GFX stuff
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*/
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#include "clearstate_defs.h"
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#include "amdgpu_ring.h"
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#include "amdgpu_rlc.h"
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#include "amdgpu_imu.h"
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#include "soc15.h"
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#include "amdgpu_ras.h"
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/* GFX current status */
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#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
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#define AMDGPU_GFX_SAFE_MODE 0x00000001L
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#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
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#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
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#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
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#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
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#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
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enum amdgpu_gfx_pipe_priority {
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AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
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AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
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};
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#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
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#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
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struct amdgpu_mec {
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struct amdgpu_bo *hpd_eop_obj;
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u64 hpd_eop_gpu_addr;
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struct amdgpu_bo *mec_fw_obj;
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u64 mec_fw_gpu_addr;
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struct amdgpu_bo *mec_fw_data_obj;
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u64 mec_fw_data_gpu_addr;
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u32 num_mec;
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u32 num_pipe_per_mec;
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u32 num_queue_per_pipe;
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void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
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/* These are the resources for which amdgpu takes ownership */
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DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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};
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enum amdgpu_unmap_queues_action {
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PREEMPT_QUEUES = 0,
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RESET_QUEUES,
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DISABLE_PROCESS_QUEUES,
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PREEMPT_QUEUES_NO_UNMAP,
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};
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struct kiq_pm4_funcs {
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/* Support ASIC-specific kiq pm4 packets*/
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void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
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uint64_t queue_mask);
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void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring);
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void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring,
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enum amdgpu_unmap_queues_action action,
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u64 gpu_addr, u64 seq);
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void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
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struct amdgpu_ring *ring,
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u64 addr,
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u64 seq);
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void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
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uint16_t pasid, uint32_t flush_type,
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bool all_hub);
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/* Packet sizes */
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int set_resources_size;
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int map_queues_size;
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int unmap_queues_size;
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int query_status_size;
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int invalidate_tlbs_size;
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};
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struct amdgpu_kiq {
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u64 eop_gpu_addr;
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struct amdgpu_bo *eop_obj;
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spinlock_t ring_lock;
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struct amdgpu_ring ring;
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struct amdgpu_irq_src irq;
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const struct kiq_pm4_funcs *pmf;
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};
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/*
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* GFX configurations
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*/
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#define AMDGPU_GFX_MAX_SE 4
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#define AMDGPU_GFX_MAX_SH_PER_SE 2
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struct amdgpu_rb_config {
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uint32_t rb_backend_disable;
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uint32_t user_rb_backend_disable;
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uint32_t raster_config;
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uint32_t raster_config_1;
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};
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struct gb_addr_config {
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uint16_t pipe_interleave_size;
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uint8_t num_pipes;
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uint8_t max_compress_frags;
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uint8_t num_banks;
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uint8_t num_se;
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uint8_t num_rb_per_se;
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uint8_t num_pkrs;
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};
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struct amdgpu_gfx_config {
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unsigned max_shader_engines;
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unsigned max_tile_pipes;
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unsigned max_cu_per_sh;
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unsigned max_sh_per_se;
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unsigned max_backends_per_se;
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unsigned max_texture_channel_caches;
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unsigned max_gprs;
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unsigned max_gs_threads;
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unsigned max_hw_contexts;
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unsigned sc_prim_fifo_size_frontend;
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unsigned sc_prim_fifo_size_backend;
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unsigned sc_hiz_tile_fifo_size;
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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unsigned backend_enable_mask;
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unsigned mem_max_burst_length_bytes;
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unsigned mem_row_size_in_kb;
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unsigned shader_engine_tile_size;
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unsigned num_gpus;
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unsigned multi_gpu_tile_size;
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unsigned mc_arb_ramcfg;
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unsigned num_banks;
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unsigned num_ranks;
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unsigned gb_addr_config;
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unsigned num_rbs;
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unsigned gs_vgt_table_depth;
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unsigned gs_prim_buffer_depth;
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uint32_t tile_mode_array[32];
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uint32_t macrotile_mode_array[16];
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struct gb_addr_config gb_addr_config_fields;
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struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
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/* gfx configure feature */
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uint32_t double_offchip_lds_buf;
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/* cached value of DB_DEBUG2 */
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uint32_t db_debug2;
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/* gfx10 specific config */
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uint32_t num_sc_per_sh;
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uint32_t num_packer_per_sc;
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uint32_t pa_sc_tile_steering_override;
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uint64_t tcc_disabled_mask;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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uint32_t gc_num_tcp_per_wpg;
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uint32_t gc_tcp_l1_size;
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uint32_t gc_num_sqc_per_wgp;
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uint32_t gc_l1_instruction_cache_size_per_sqc;
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uint32_t gc_l1_data_cache_size_per_sqc;
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uint32_t gc_gl1c_per_sa;
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uint32_t gc_gl1c_size_per_instance;
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uint32_t gc_gl2c_per_gpu;
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};
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struct amdgpu_cu_info {
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uint32_t simd_per_cu;
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uint32_t max_waves_per_simd;
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uint32_t wave_front_size;
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uint32_t max_scratch_slots_per_cu;
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uint32_t lds_size;
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/* total active CU number */
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uint32_t number;
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uint32_t ao_cu_mask;
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uint32_t ao_cu_bitmap[4][4];
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uint32_t bitmap[4][4];
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};
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struct amdgpu_gfx_ras {
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struct amdgpu_ras_block_object ras_block;
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void (*enable_watchdog_timer)(struct amdgpu_device *adev);
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bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
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};
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struct amdgpu_gfx_funcs {
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/* get the gpu clock counter */
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uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
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void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
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u32 sh_num, u32 instance);
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void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
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uint32_t wave, uint32_t *dst, int *no_fields);
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void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
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uint32_t wave, uint32_t thread, uint32_t start,
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uint32_t size, uint32_t *dst);
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void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
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uint32_t wave, uint32_t start, uint32_t size,
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uint32_t *dst);
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void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
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u32 queue, u32 vmid);
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void (*init_spm_golden)(struct amdgpu_device *adev);
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void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
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};
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struct sq_work {
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struct work_struct work;
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unsigned ih_data;
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};
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struct amdgpu_pfp {
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struct amdgpu_bo *pfp_fw_obj;
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uint64_t pfp_fw_gpu_addr;
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uint32_t *pfp_fw_ptr;
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struct amdgpu_bo *pfp_fw_data_obj;
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uint64_t pfp_fw_data_gpu_addr;
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uint32_t *pfp_fw_data_ptr;
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};
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struct amdgpu_ce {
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struct amdgpu_bo *ce_fw_obj;
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uint64_t ce_fw_gpu_addr;
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uint32_t *ce_fw_ptr;
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};
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struct amdgpu_me {
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struct amdgpu_bo *me_fw_obj;
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uint64_t me_fw_gpu_addr;
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uint32_t *me_fw_ptr;
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struct amdgpu_bo *me_fw_data_obj;
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uint64_t me_fw_data_gpu_addr;
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uint32_t *me_fw_data_ptr;
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uint32_t num_me;
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uint32_t num_pipe_per_me;
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uint32_t num_queue_per_pipe;
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void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
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/* These are the resources for which amdgpu takes ownership */
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DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
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};
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struct amdgpu_gfx {
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struct mutex gpu_clock_mutex;
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struct amdgpu_gfx_config config;
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struct amdgpu_rlc rlc;
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struct amdgpu_pfp pfp;
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struct amdgpu_ce ce;
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struct amdgpu_me me;
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struct amdgpu_mec mec;
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struct amdgpu_kiq kiq;
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struct amdgpu_imu imu;
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bool rs64_enable; /* firmware format */
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const struct firmware *me_fw; /* ME firmware */
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uint32_t me_fw_version;
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const struct firmware *pfp_fw; /* PFP firmware */
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uint32_t pfp_fw_version;
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const struct firmware *ce_fw; /* CE firmware */
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uint32_t ce_fw_version;
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const struct firmware *rlc_fw; /* RLC firmware */
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uint32_t rlc_fw_version;
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const struct firmware *mec_fw; /* MEC firmware */
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uint32_t mec_fw_version;
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const struct firmware *mec2_fw; /* MEC2 firmware */
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uint32_t mec2_fw_version;
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const struct firmware *imu_fw; /* IMU firmware */
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uint32_t imu_fw_version;
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uint32_t me_feature_version;
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uint32_t ce_feature_version;
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uint32_t pfp_feature_version;
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uint32_t rlc_feature_version;
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uint32_t rlc_srlc_fw_version;
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uint32_t rlc_srlc_feature_version;
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uint32_t rlc_srlg_fw_version;
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uint32_t rlc_srlg_feature_version;
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uint32_t rlc_srls_fw_version;
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uint32_t rlc_srls_feature_version;
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uint32_t rlcp_ucode_version;
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uint32_t rlcp_ucode_feature_version;
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uint32_t rlcv_ucode_version;
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uint32_t rlcv_ucode_feature_version;
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uint32_t mec_feature_version;
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uint32_t mec2_feature_version;
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bool mec_fw_write_wait;
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bool me_fw_write_wait;
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bool cp_fw_write_wait;
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struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
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unsigned num_gfx_rings;
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struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
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unsigned num_compute_rings;
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struct amdgpu_irq_src eop_irq;
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struct amdgpu_irq_src priv_reg_irq;
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struct amdgpu_irq_src priv_inst_irq;
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struct amdgpu_irq_src cp_ecc_error_irq;
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struct amdgpu_irq_src sq_irq;
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struct sq_work sq_work;
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/* gfx status */
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uint32_t gfx_current_status;
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/* ce ram size*/
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unsigned ce_ram_size;
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struct amdgpu_cu_info cu_info;
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const struct amdgpu_gfx_funcs *funcs;
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/* reset mask */
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uint32_t grbm_soft_reset;
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uint32_t srbm_soft_reset;
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/* gfx off */
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bool gfx_off_state; /* true: enabled, false: disabled */
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struct mutex gfx_off_mutex; /* mutex to change gfxoff state */
|
||
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uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
|
||
|
|
struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
|
||
|
|
uint32_t gfx_off_residency; /* last logged residency */
|
||
|
|
uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
|
||
|
|
|
||
|
|
/* pipe reservation */
|
||
|
|
struct mutex pipe_reserve_mutex;
|
||
|
|
DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
|
||
|
|
|
||
|
|
/*ras */
|
||
|
|
struct ras_common_if *ras_if;
|
||
|
|
struct amdgpu_gfx_ras *ras;
|
||
|
|
|
||
|
|
bool is_poweron;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
|
||
|
|
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
|
||
|
|
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
|
||
|
|
#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_gfx_create_bitmask - create a bitmask
|
||
|
|
*
|
||
|
|
* @bit_width: length of the mask
|
||
|
|
*
|
||
|
|
* create a variable length bit mask.
|
||
|
|
* Returns the bitmask.
|
||
|
|
*/
|
||
|
|
static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
|
||
|
|
{
|
||
|
|
return (u32)((1ULL << bit_width) - 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
|
||
|
|
unsigned max_sh);
|
||
|
|
|
||
|
|
int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_ring *ring,
|
||
|
|
struct amdgpu_irq_src *irq);
|
||
|
|
|
||
|
|
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
|
||
|
|
|
||
|
|
void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
|
||
|
|
int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
|
||
|
|
unsigned hpd_size);
|
||
|
|
|
||
|
|
int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
|
||
|
|
unsigned mqd_size);
|
||
|
|
void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
|
||
|
|
int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
|
||
|
|
int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
|
||
|
|
|
||
|
|
void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
|
||
|
|
void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
|
||
|
|
|
||
|
|
int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
|
||
|
|
int pipe, int queue);
|
||
|
|
void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
|
||
|
|
int *mec, int *pipe, int *queue);
|
||
|
|
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
|
||
|
|
int pipe, int queue);
|
||
|
|
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_ring *ring);
|
||
|
|
bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_ring *ring);
|
||
|
|
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
|
||
|
|
int pipe, int queue);
|
||
|
|
void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
|
||
|
|
int *me, int *pipe, int *queue);
|
||
|
|
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
|
||
|
|
int pipe, int queue);
|
||
|
|
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
|
||
|
|
int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
|
||
|
|
int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
|
||
|
|
void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
|
||
|
|
int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
|
||
|
|
int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
|
||
|
|
int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
|
||
|
|
int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
|
||
|
|
void *err_data,
|
||
|
|
struct amdgpu_iv_entry *entry);
|
||
|
|
int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
|
||
|
|
struct amdgpu_irq_src *source,
|
||
|
|
struct amdgpu_iv_entry *entry);
|
||
|
|
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
|
||
|
|
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
|
||
|
|
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
|
||
|
|
void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
|
||
|
|
|
||
|
|
#endif
|