121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_HITACHI_SE_H
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#define __ASM_SH_HITACHI_SE_H
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/*
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* linux/include/asm-sh/hitachi_se.h
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* Hitachi SolutionEngine support
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*/
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#include <linux/sh_intc.h>
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/* Box specific addresses. */
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#define PA_ROM 0x00000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
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#define PA_FROM 0x01000000 /* EPROM */
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#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
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#define PA_EXT1 0x04000000
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#define PA_EXT1_SIZE 0x04000000
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#define PA_EXT2 0x08000000
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#define PA_EXT2_SIZE 0x04000000
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#define PA_SDRAM 0x0c000000
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#define PA_SDRAM_SIZE 0x04000000
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#define PA_EXT4 0x12000000
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#define PA_EXT4_SIZE 0x02000000
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#define PA_EXT5 0x14000000
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#define PA_EXT5_SIZE 0x04000000
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#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
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#define PA_83902 0xb0000000 /* DP83902A */
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#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */
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#define PA_83902_RST 0xb0080000 /* DP83902A reset port */
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#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */
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#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
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#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
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#define PA_LED 0xb0c00000 /* LED */
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define PA_BCR 0xb0e00000
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#else
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#define PA_BCR 0xb1400000 /* FPGA */
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#endif
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#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
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#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define BCR_ILCRA (PA_BCR + 0)
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#define BCR_ILCRB (PA_BCR + 2)
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#define BCR_ILCRC (PA_BCR + 4)
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#define BCR_ILCRD (PA_BCR + 6)
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#define BCR_ILCRE (PA_BCR + 8)
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#define BCR_ILCRF (PA_BCR + 10)
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#define BCR_ILCRG (PA_BCR + 12)
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#if defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define INTC_IRR0 0xa4000004UL
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#define INTC_IRR1 0xa4000006UL
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#define INTC_IRR2 0xa4000008UL
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#define INTC_ICR0 0xfffffee0UL
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#define INTC_ICR1 0xa4000010UL
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#define INTC_ICR2 0xa4000012UL
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#define INTC_INTER 0xa4000014UL
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#define INTC_IPRC 0xa4000016UL
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#define INTC_IPRD 0xa4000018UL
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#define INTC_IPRE 0xa400001aUL
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#define IRQ0_IRQ evt2irq(0x600)
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#define IRQ1_IRQ evt2irq(0x620)
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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#define IRQ_STNIC evt2irq(0x380)
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#define IRQ_CFCARD evt2irq(0x3c0)
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#else
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#define IRQ_STNIC evt2irq(0x340)
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#define IRQ_CFCARD evt2irq(0x2e0)
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#endif
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/* SH Ether support (SH7710/SH7712) */
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/* Base address */
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#define SH_ETH0_BASE 0xA7000000
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#define SH_ETH1_BASE 0xA7000400
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#define SH_TSU_BASE 0xA7000800
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/* PHY ID */
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define PHY_ID 0x00
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#elif defined(CONFIG_CPU_SUBTYPE_SH7712)
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# define PHY_ID 0x01
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#endif
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/* Ether IRQ */
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#define SH_ETH0_IRQ evt2irq(0xc00)
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#define SH_ETH1_IRQ evt2irq(0xc20)
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#define SH_TSU_IRQ evt2irq(0xc40)
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void init_se_IRQ(void);
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#define __IO_PREFIX se
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_HITACHI_SE_H */
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