403 lines
10 KiB
C
403 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#include <linux/bitmap.h>
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#include <linux/cpumask.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/kvm_host.h>
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#include <asm/cacheflush.h>
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#include <asm/csr.h>
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#include <asm/hwcap.h>
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#include <asm/insn-def.h>
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#define has_svinval() \
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static_branch_unlikely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVINVAL])
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void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid,
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gpa_t gpa, gpa_t gpsz,
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unsigned long order)
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{
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gpa_t pos;
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if (PTRS_PER_PTE < (gpsz >> order)) {
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kvm_riscv_local_hfence_gvma_vmid_all(vmid);
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return;
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}
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if (has_svinval()) {
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asm volatile (SFENCE_W_INVAL() ::: "memory");
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for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
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asm volatile (HINVAL_GVMA(%0, %1)
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: : "r" (pos >> 2), "r" (vmid) : "memory");
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asm volatile (SFENCE_INVAL_IR() ::: "memory");
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} else {
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for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
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asm volatile (HFENCE_GVMA(%0, %1)
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: : "r" (pos >> 2), "r" (vmid) : "memory");
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}
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}
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void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid)
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{
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asm volatile(HFENCE_GVMA(zero, %0) : : "r" (vmid) : "memory");
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}
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void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz,
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unsigned long order)
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{
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gpa_t pos;
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if (PTRS_PER_PTE < (gpsz >> order)) {
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kvm_riscv_local_hfence_gvma_all();
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return;
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}
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if (has_svinval()) {
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asm volatile (SFENCE_W_INVAL() ::: "memory");
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for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
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asm volatile(HINVAL_GVMA(%0, zero)
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: : "r" (pos >> 2) : "memory");
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asm volatile (SFENCE_INVAL_IR() ::: "memory");
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} else {
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for (pos = gpa; pos < (gpa + gpsz); pos += BIT(order))
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asm volatile(HFENCE_GVMA(%0, zero)
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: : "r" (pos >> 2) : "memory");
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}
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}
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void kvm_riscv_local_hfence_gvma_all(void)
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{
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asm volatile(HFENCE_GVMA(zero, zero) : : : "memory");
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}
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void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid,
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unsigned long asid,
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unsigned long gva,
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unsigned long gvsz,
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unsigned long order)
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{
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unsigned long pos, hgatp;
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if (PTRS_PER_PTE < (gvsz >> order)) {
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kvm_riscv_local_hfence_vvma_asid_all(vmid, asid);
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return;
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}
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hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
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if (has_svinval()) {
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asm volatile (SFENCE_W_INVAL() ::: "memory");
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for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
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asm volatile(HINVAL_VVMA(%0, %1)
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: : "r" (pos), "r" (asid) : "memory");
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asm volatile (SFENCE_INVAL_IR() ::: "memory");
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} else {
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for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
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asm volatile(HFENCE_VVMA(%0, %1)
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: : "r" (pos), "r" (asid) : "memory");
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}
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csr_write(CSR_HGATP, hgatp);
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}
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void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid,
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unsigned long asid)
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{
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unsigned long hgatp;
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hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
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asm volatile(HFENCE_VVMA(zero, %0) : : "r" (asid) : "memory");
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csr_write(CSR_HGATP, hgatp);
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}
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void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid,
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unsigned long gva, unsigned long gvsz,
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unsigned long order)
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{
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unsigned long pos, hgatp;
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if (PTRS_PER_PTE < (gvsz >> order)) {
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kvm_riscv_local_hfence_vvma_all(vmid);
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return;
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}
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hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
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if (has_svinval()) {
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asm volatile (SFENCE_W_INVAL() ::: "memory");
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for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
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asm volatile(HINVAL_VVMA(%0, zero)
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: : "r" (pos) : "memory");
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asm volatile (SFENCE_INVAL_IR() ::: "memory");
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} else {
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for (pos = gva; pos < (gva + gvsz); pos += BIT(order))
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asm volatile(HFENCE_VVMA(%0, zero)
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: : "r" (pos) : "memory");
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}
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csr_write(CSR_HGATP, hgatp);
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}
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void kvm_riscv_local_hfence_vvma_all(unsigned long vmid)
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{
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unsigned long hgatp;
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hgatp = csr_swap(CSR_HGATP, vmid << HGATP_VMID_SHIFT);
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asm volatile(HFENCE_VVMA(zero, zero) : : : "memory");
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csr_write(CSR_HGATP, hgatp);
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}
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void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu)
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{
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unsigned long vmid;
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if (!kvm_riscv_gstage_vmid_bits() ||
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vcpu->arch.last_exit_cpu == vcpu->cpu)
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return;
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/*
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* On RISC-V platforms with hardware VMID support, we share same
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* VMID for all VCPUs of a particular Guest/VM. This means we might
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* have stale G-stage TLB entries on the current Host CPU due to
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* some other VCPU of the same Guest which ran previously on the
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* current Host CPU.
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*
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* To cleanup stale TLB entries, we simply flush all G-stage TLB
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* entries by VMID whenever underlying Host CPU changes for a VCPU.
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*/
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vmid = READ_ONCE(vcpu->kvm->arch.vmid.vmid);
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kvm_riscv_local_hfence_gvma_vmid_all(vmid);
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}
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void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu)
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{
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local_flush_icache_all();
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}
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void kvm_riscv_hfence_gvma_vmid_all_process(struct kvm_vcpu *vcpu)
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{
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struct kvm_vmid *vmid;
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vmid = &vcpu->kvm->arch.vmid;
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kvm_riscv_local_hfence_gvma_vmid_all(READ_ONCE(vmid->vmid));
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}
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void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu)
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{
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struct kvm_vmid *vmid;
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vmid = &vcpu->kvm->arch.vmid;
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kvm_riscv_local_hfence_vvma_all(READ_ONCE(vmid->vmid));
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}
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static bool vcpu_hfence_dequeue(struct kvm_vcpu *vcpu,
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struct kvm_riscv_hfence *out_data)
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{
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bool ret = false;
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struct kvm_vcpu_arch *varch = &vcpu->arch;
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spin_lock(&varch->hfence_lock);
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if (varch->hfence_queue[varch->hfence_head].type) {
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memcpy(out_data, &varch->hfence_queue[varch->hfence_head],
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sizeof(*out_data));
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varch->hfence_queue[varch->hfence_head].type = 0;
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varch->hfence_head++;
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if (varch->hfence_head == KVM_RISCV_VCPU_MAX_HFENCE)
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varch->hfence_head = 0;
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ret = true;
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}
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spin_unlock(&varch->hfence_lock);
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return ret;
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}
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static bool vcpu_hfence_enqueue(struct kvm_vcpu *vcpu,
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const struct kvm_riscv_hfence *data)
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{
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bool ret = false;
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struct kvm_vcpu_arch *varch = &vcpu->arch;
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spin_lock(&varch->hfence_lock);
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if (!varch->hfence_queue[varch->hfence_tail].type) {
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memcpy(&varch->hfence_queue[varch->hfence_tail],
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data, sizeof(*data));
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varch->hfence_tail++;
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if (varch->hfence_tail == KVM_RISCV_VCPU_MAX_HFENCE)
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varch->hfence_tail = 0;
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ret = true;
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}
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spin_unlock(&varch->hfence_lock);
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return ret;
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}
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void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu)
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{
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struct kvm_riscv_hfence d = { 0 };
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struct kvm_vmid *v = &vcpu->kvm->arch.vmid;
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while (vcpu_hfence_dequeue(vcpu, &d)) {
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switch (d.type) {
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case KVM_RISCV_HFENCE_UNKNOWN:
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break;
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case KVM_RISCV_HFENCE_GVMA_VMID_GPA:
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kvm_riscv_local_hfence_gvma_vmid_gpa(
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READ_ONCE(v->vmid),
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d.addr, d.size, d.order);
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break;
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case KVM_RISCV_HFENCE_VVMA_ASID_GVA:
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kvm_riscv_local_hfence_vvma_asid_gva(
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READ_ONCE(v->vmid), d.asid,
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d.addr, d.size, d.order);
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break;
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case KVM_RISCV_HFENCE_VVMA_ASID_ALL:
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kvm_riscv_local_hfence_vvma_asid_all(
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READ_ONCE(v->vmid), d.asid);
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break;
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case KVM_RISCV_HFENCE_VVMA_GVA:
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kvm_riscv_local_hfence_vvma_gva(
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READ_ONCE(v->vmid),
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d.addr, d.size, d.order);
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break;
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default:
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break;
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}
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}
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}
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static void make_xfence_request(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned int req, unsigned int fallback_req,
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const struct kvm_riscv_hfence *data)
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{
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unsigned long i;
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struct kvm_vcpu *vcpu;
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unsigned int actual_req = req;
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DECLARE_BITMAP(vcpu_mask, KVM_MAX_VCPUS);
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bitmap_clear(vcpu_mask, 0, KVM_MAX_VCPUS);
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (hbase != -1UL) {
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if (vcpu->vcpu_id < hbase)
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continue;
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if (!(hmask & (1UL << (vcpu->vcpu_id - hbase))))
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continue;
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}
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bitmap_set(vcpu_mask, i, 1);
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if (!data || !data->type)
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continue;
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/*
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* Enqueue hfence data to VCPU hfence queue. If we don't
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* have space in the VCPU hfence queue then fallback to
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* a more conservative hfence request.
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*/
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if (!vcpu_hfence_enqueue(vcpu, data))
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actual_req = fallback_req;
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}
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kvm_make_vcpus_request_mask(kvm, actual_req, vcpu_mask);
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}
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void kvm_riscv_fence_i(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask)
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{
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_FENCE_I,
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KVM_REQ_FENCE_I, NULL);
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}
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void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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gpa_t gpa, gpa_t gpsz,
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unsigned long order)
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{
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struct kvm_riscv_hfence data;
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data.type = KVM_RISCV_HFENCE_GVMA_VMID_GPA;
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data.asid = 0;
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data.addr = gpa;
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data.size = gpsz;
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data.order = order;
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
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KVM_REQ_HFENCE_GVMA_VMID_ALL, &data);
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}
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void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask)
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{
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE_GVMA_VMID_ALL,
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KVM_REQ_HFENCE_GVMA_VMID_ALL, NULL);
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}
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void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long gva, unsigned long gvsz,
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unsigned long order, unsigned long asid)
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{
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struct kvm_riscv_hfence data;
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data.type = KVM_RISCV_HFENCE_VVMA_ASID_GVA;
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data.asid = asid;
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data.addr = gva;
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data.size = gvsz;
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data.order = order;
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
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KVM_REQ_HFENCE_VVMA_ALL, &data);
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}
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void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long asid)
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{
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struct kvm_riscv_hfence data;
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data.type = KVM_RISCV_HFENCE_VVMA_ASID_ALL;
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data.asid = asid;
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data.addr = data.size = data.order = 0;
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
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KVM_REQ_HFENCE_VVMA_ALL, &data);
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}
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void kvm_riscv_hfence_vvma_gva(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long gva, unsigned long gvsz,
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unsigned long order)
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{
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struct kvm_riscv_hfence data;
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data.type = KVM_RISCV_HFENCE_VVMA_GVA;
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data.asid = 0;
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data.addr = gva;
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data.size = gvsz;
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data.order = order;
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE,
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KVM_REQ_HFENCE_VVMA_ALL, &data);
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}
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void kvm_riscv_hfence_vvma_all(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask)
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{
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make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE_VVMA_ALL,
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KVM_REQ_HFENCE_VVMA_ALL, NULL);
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}
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