570 lines
14 KiB
C
570 lines
14 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_INST_H
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#define _ASM_INST_H
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#include <linux/types.h>
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#include <asm/asm.h>
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#define INSN_BREAK 0x002a0000
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#define ADDR_IMMMASK_LU52ID 0xFFF0000000000000
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#define ADDR_IMMMASK_LU32ID 0x000FFFFF00000000
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#define ADDR_IMMMASK_ADDU16ID 0x00000000FFFF0000
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#define ADDR_IMMSHIFT_LU52ID 52
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#define ADDR_IMMSHIFT_LU32ID 32
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#define ADDR_IMMSHIFT_ADDU16ID 16
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#define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
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enum reg0i26_op {
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b_op = 0x14,
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bl_op = 0x15,
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};
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enum reg1i20_op {
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lu12iw_op = 0x0a,
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lu32id_op = 0x0b,
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pcaddu12i_op = 0x0e,
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pcaddu18i_op = 0x0f,
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};
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enum reg1i21_op {
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beqz_op = 0x10,
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bnez_op = 0x11,
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};
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enum reg2_op {
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revb2h_op = 0x0c,
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revb4h_op = 0x0d,
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revb2w_op = 0x0e,
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revbd_op = 0x0f,
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revh2w_op = 0x10,
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revhd_op = 0x11,
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};
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enum reg2i5_op {
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slliw_op = 0x81,
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srliw_op = 0x89,
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sraiw_op = 0x91,
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};
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enum reg2i6_op {
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sllid_op = 0x41,
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srlid_op = 0x45,
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sraid_op = 0x49,
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};
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enum reg2i12_op {
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addiw_op = 0x0a,
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addid_op = 0x0b,
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lu52id_op = 0x0c,
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andi_op = 0x0d,
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ori_op = 0x0e,
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xori_op = 0x0f,
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ldb_op = 0xa0,
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ldh_op = 0xa1,
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ldw_op = 0xa2,
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ldd_op = 0xa3,
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stb_op = 0xa4,
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sth_op = 0xa5,
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stw_op = 0xa6,
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std_op = 0xa7,
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ldbu_op = 0xa8,
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ldhu_op = 0xa9,
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ldwu_op = 0xaa,
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};
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enum reg2i14_op {
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llw_op = 0x20,
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scw_op = 0x21,
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lld_op = 0x22,
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scd_op = 0x23,
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ldptrw_op = 0x24,
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stptrw_op = 0x25,
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ldptrd_op = 0x26,
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stptrd_op = 0x27,
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};
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enum reg2i16_op {
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jirl_op = 0x13,
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beq_op = 0x16,
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bne_op = 0x17,
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blt_op = 0x18,
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bge_op = 0x19,
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bltu_op = 0x1a,
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bgeu_op = 0x1b,
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};
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enum reg2bstrd_op {
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bstrinsd_op = 0x2,
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bstrpickd_op = 0x3,
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};
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enum reg3_op {
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addw_op = 0x20,
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addd_op = 0x21,
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subw_op = 0x22,
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subd_op = 0x23,
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nor_op = 0x28,
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and_op = 0x29,
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or_op = 0x2a,
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xor_op = 0x2b,
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orn_op = 0x2c,
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andn_op = 0x2d,
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sllw_op = 0x2e,
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srlw_op = 0x2f,
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sraw_op = 0x30,
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slld_op = 0x31,
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srld_op = 0x32,
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srad_op = 0x33,
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mulw_op = 0x38,
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mulhw_op = 0x39,
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mulhwu_op = 0x3a,
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muld_op = 0x3b,
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mulhd_op = 0x3c,
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mulhdu_op = 0x3d,
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divw_op = 0x40,
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modw_op = 0x41,
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divwu_op = 0x42,
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modwu_op = 0x43,
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divd_op = 0x44,
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modd_op = 0x45,
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divdu_op = 0x46,
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moddu_op = 0x47,
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ldxb_op = 0x7000,
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ldxh_op = 0x7008,
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ldxw_op = 0x7010,
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ldxd_op = 0x7018,
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stxb_op = 0x7020,
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stxh_op = 0x7028,
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stxw_op = 0x7030,
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stxd_op = 0x7038,
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ldxbu_op = 0x7040,
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ldxhu_op = 0x7048,
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ldxwu_op = 0x7050,
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amswapw_op = 0x70c0,
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amswapd_op = 0x70c1,
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amaddw_op = 0x70c2,
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amaddd_op = 0x70c3,
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amandw_op = 0x70c4,
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amandd_op = 0x70c5,
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amorw_op = 0x70c6,
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amord_op = 0x70c7,
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amxorw_op = 0x70c8,
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amxord_op = 0x70c9,
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};
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enum reg3sa2_op {
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alslw_op = 0x02,
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alslwu_op = 0x03,
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alsld_op = 0x16,
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};
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struct reg0i26_format {
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unsigned int immediate_h : 10;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg1i20_format {
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unsigned int rd : 5;
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unsigned int immediate : 20;
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unsigned int opcode : 7;
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};
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struct reg1i21_format {
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unsigned int immediate_h : 5;
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unsigned int rj : 5;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg2_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int opcode : 22;
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};
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struct reg2i5_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 5;
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unsigned int opcode : 17;
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};
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struct reg2i6_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 6;
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unsigned int opcode : 16;
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};
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struct reg2i12_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 12;
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unsigned int opcode : 10;
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};
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struct reg2i14_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 14;
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unsigned int opcode : 8;
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};
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struct reg2i16_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 16;
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unsigned int opcode : 6;
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};
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struct reg2bstrd_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int lsbd : 6;
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unsigned int msbd : 6;
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unsigned int opcode : 10;
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};
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struct reg3_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int rk : 5;
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unsigned int opcode : 17;
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};
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struct reg3sa2_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int rk : 5;
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unsigned int immediate : 2;
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unsigned int opcode : 15;
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};
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union loongarch_instruction {
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unsigned int word;
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struct reg0i26_format reg0i26_format;
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struct reg1i20_format reg1i20_format;
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struct reg1i21_format reg1i21_format;
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struct reg2_format reg2_format;
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struct reg2i5_format reg2i5_format;
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struct reg2i6_format reg2i6_format;
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struct reg2i12_format reg2i12_format;
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struct reg2i14_format reg2i14_format;
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struct reg2i16_format reg2i16_format;
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struct reg2bstrd_format reg2bstrd_format;
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struct reg3_format reg3_format;
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struct reg3sa2_format reg3sa2_format;
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};
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#define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
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enum loongarch_gpr {
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LOONGARCH_GPR_ZERO = 0,
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LOONGARCH_GPR_RA = 1,
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LOONGARCH_GPR_TP = 2,
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LOONGARCH_GPR_SP = 3,
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LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
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LOONGARCH_GPR_A1, /* Reused as V1 for return value */
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LOONGARCH_GPR_A2,
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LOONGARCH_GPR_A3,
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LOONGARCH_GPR_A4,
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LOONGARCH_GPR_A5,
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LOONGARCH_GPR_A6,
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LOONGARCH_GPR_A7,
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LOONGARCH_GPR_T0 = 12,
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LOONGARCH_GPR_T1,
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LOONGARCH_GPR_T2,
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LOONGARCH_GPR_T3,
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LOONGARCH_GPR_T4,
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LOONGARCH_GPR_T5,
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LOONGARCH_GPR_T6,
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LOONGARCH_GPR_T7,
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LOONGARCH_GPR_T8,
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LOONGARCH_GPR_FP = 22,
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LOONGARCH_GPR_S0 = 23,
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LOONGARCH_GPR_S1,
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LOONGARCH_GPR_S2,
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LOONGARCH_GPR_S3,
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LOONGARCH_GPR_S4,
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LOONGARCH_GPR_S5,
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LOONGARCH_GPR_S6,
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LOONGARCH_GPR_S7,
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LOONGARCH_GPR_S8,
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LOONGARCH_GPR_MAX
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};
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#define is_imm12_negative(val) is_imm_negative(val, 12)
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static inline bool is_imm_negative(unsigned long val, unsigned int bit)
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{
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return val & (1UL << (bit - 1));
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}
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static inline bool is_branch_ins(union loongarch_instruction *ip)
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{
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return ip->reg1i21_format.opcode >= beqz_op &&
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ip->reg1i21_format.opcode <= bgeu_op;
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}
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static inline bool is_ra_save_ins(union loongarch_instruction *ip)
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{
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/* st.d $ra, $sp, offset */
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return ip->reg2i12_format.opcode == std_op &&
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ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
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ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
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!is_imm12_negative(ip->reg2i12_format.immediate);
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}
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static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
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{
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/* addi.d $sp, $sp, -imm */
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return ip->reg2i12_format.opcode == addid_op &&
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ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
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ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
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is_imm12_negative(ip->reg2i12_format.immediate);
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}
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u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
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u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
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u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest);
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static inline bool signed_imm_check(long val, unsigned int bit)
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{
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return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));
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}
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static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
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{
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return val < (1UL << bit);
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}
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#define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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int offset) \
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{ \
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unsigned int immediate_l, immediate_h; \
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\
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immediate_l = offset & 0xffff; \
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offset >>= 16; \
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immediate_h = offset & 0x3ff; \
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\
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insn->reg0i26_format.opcode = OP; \
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insn->reg0i26_format.immediate_l = immediate_l; \
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insn->reg0i26_format.immediate_h = immediate_h; \
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}
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DEF_EMIT_REG0I26_FORMAT(b, b_op)
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#define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, int imm) \
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{ \
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insn->reg1i20_format.opcode = OP; \
|
||
|
|
insn->reg1i20_format.immediate = imm; \
|
||
|
|
insn->reg1i20_format.rd = rd; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
|
||
|
|
DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
|
||
|
|
DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj) \
|
||
|
|
{ \
|
||
|
|
insn->reg2_format.opcode = OP; \
|
||
|
|
insn->reg2_format.rd = rd; \
|
||
|
|
insn->reg2_format.rj = rj; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
|
||
|
|
DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
|
||
|
|
DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
int imm) \
|
||
|
|
{ \
|
||
|
|
insn->reg2i5_format.opcode = OP; \
|
||
|
|
insn->reg2i5_format.immediate = imm; \
|
||
|
|
insn->reg2i5_format.rd = rd; \
|
||
|
|
insn->reg2i5_format.rj = rj; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
|
||
|
|
DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
|
||
|
|
DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
int imm) \
|
||
|
|
{ \
|
||
|
|
insn->reg2i6_format.opcode = OP; \
|
||
|
|
insn->reg2i6_format.immediate = imm; \
|
||
|
|
insn->reg2i6_format.rd = rd; \
|
||
|
|
insn->reg2i6_format.rj = rj; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
|
||
|
|
DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
|
||
|
|
DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
int imm) \
|
||
|
|
{ \
|
||
|
|
insn->reg2i12_format.opcode = OP; \
|
||
|
|
insn->reg2i12_format.immediate = imm; \
|
||
|
|
insn->reg2i12_format.rd = rd; \
|
||
|
|
insn->reg2i12_format.rj = rj; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
|
||
|
|
DEF_EMIT_REG2I12_FORMAT(std, std_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
int imm) \
|
||
|
|
{ \
|
||
|
|
insn->reg2i14_format.opcode = OP; \
|
||
|
|
insn->reg2i14_format.immediate = imm; \
|
||
|
|
insn->reg2i14_format.rd = rd; \
|
||
|
|
insn->reg2i14_format.rj = rj; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
|
||
|
|
DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
int offset) \
|
||
|
|
{ \
|
||
|
|
insn->reg2i16_format.opcode = OP; \
|
||
|
|
insn->reg2i16_format.immediate = offset; \
|
||
|
|
insn->reg2i16_format.rj = rj; \
|
||
|
|
insn->reg2i16_format.rd = rd; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
|
||
|
|
DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
int msbd, \
|
||
|
|
int lsbd) \
|
||
|
|
{ \
|
||
|
|
insn->reg2bstrd_format.opcode = OP; \
|
||
|
|
insn->reg2bstrd_format.msbd = msbd; \
|
||
|
|
insn->reg2bstrd_format.lsbd = lsbd; \
|
||
|
|
insn->reg2bstrd_format.rj = rj; \
|
||
|
|
insn->reg2bstrd_format.rd = rd; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG3_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
enum loongarch_gpr rk) \
|
||
|
|
{ \
|
||
|
|
insn->reg3_format.opcode = OP; \
|
||
|
|
insn->reg3_format.rd = rd; \
|
||
|
|
insn->reg3_format.rj = rj; \
|
||
|
|
insn->reg3_format.rk = rk; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG3_FORMAT(addd, addd_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(subd, subd_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(muld, muld_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(and, and_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(or, or_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(xor, xor_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(slld, slld_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(srld, srld_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(srad, srad_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amord, amord_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
|
||
|
|
DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
|
||
|
|
|
||
|
|
#define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
|
||
|
|
static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||
|
|
enum loongarch_gpr rd, \
|
||
|
|
enum loongarch_gpr rj, \
|
||
|
|
enum loongarch_gpr rk, \
|
||
|
|
int imm) \
|
||
|
|
{ \
|
||
|
|
insn->reg3sa2_format.opcode = OP; \
|
||
|
|
insn->reg3sa2_format.immediate = imm; \
|
||
|
|
insn->reg3sa2_format.rd = rd; \
|
||
|
|
insn->reg3sa2_format.rj = rj; \
|
||
|
|
insn->reg3sa2_format.rk = rk; \
|
||
|
|
}
|
||
|
|
|
||
|
|
DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
|
||
|
|
|
||
|
|
#endif /* _ASM_INST_H */
|