126 lines
3.1 KiB
YAML
126 lines
3.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (c) 2020 NXP
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP iMX8MP Soc USB Controller
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maintainers:
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- Li Jun <jun.li@nxp.com>
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properties:
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compatible:
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const: fsl,imx8mp-dwc3
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reg:
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items:
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- description: Address and length of the register set for HSIO Block Control
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- description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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dma-ranges:
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description:
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See section 2.3.9 of the DeviceTree Specification.
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ranges: true
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interrupts:
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maxItems: 1
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description: The interrupt that is asserted when a wakeup event is
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received.
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clocks:
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description:
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A list of phandle and clock-specifier pairs for the clocks
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listed in clock-names.
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items:
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- description: system hsio root clock.
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- description: suspend clock, used for usb wakeup logic.
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clock-names:
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items:
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- const: hsio
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- const: suspend
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fsl,permanently-attached:
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type: boolean
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description:
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Indicates if the device atached to a downstream port is
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permanently attached.
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fsl,disable-port-power-control:
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type: boolean
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description:
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Indicates whether the host controller implementation includes port
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power control. Defines Bit 3 in capability register (HCCPARAMS).
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fsl,over-current-active-low:
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type: boolean
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description:
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Over current signal polarity is active low.
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fsl,power-active-low:
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type: boolean
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description:
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Power pad (PWR) polarity is active low.
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# Required child node:
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patternProperties:
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"^usb@[0-9a-f]+$":
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$ref: snps,dwc3.yaml#
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- dma-ranges
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- ranges
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- clocks
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- clock-names
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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usb3_0: usb@32f10100 {
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compatible = "fsl,imx8mp-dwc3";
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reg = <0x32f10100 0x8>,
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<0x381f0000 0x20>;
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clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "hsio", "suspend";
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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ranges;
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usb@38100000 {
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compatible = "snps,dwc3";
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reg = <0x38100000 0x10000>;
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clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
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<&clk IMX8MP_CLK_USB_CORE_REF>,
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "bus_early", "ref", "suspend";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
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assigned-clock-rates = <500000000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb3_phy0>, <&usb3_phy0>;
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phy-names = "usb2-phy", "usb3-phy";
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snps,dis-u2-freeclk-exists-quirk;
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};
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};
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