66 lines
1.6 KiB
YAML
66 lines
1.6 KiB
YAML
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||
|
%YAML 1.2
|
||
|
---
|
||
|
$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
|
||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
||
|
title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
|
||
|
|
||
|
maintainers:
|
||
|
- Dong Aisheng <aisheng.dong@nxp.com>
|
||
|
|
||
|
description: |
|
||
|
The Timer/PWM Module (TPM) supports input capture, output compare,
|
||
|
and the generation of PWM signals to control electric motor and power
|
||
|
management applications. The counter, compare and capture registers
|
||
|
are clocked by an asynchronous clock that can remain enabled in low
|
||
|
power modes. TPM can support global counter bus where one TPM drives
|
||
|
the counter bus for the others, provided bit width is the same.
|
||
|
|
||
|
properties:
|
||
|
compatible:
|
||
|
oneOf:
|
||
|
- const: fsl,imx7ulp-tpm
|
||
|
- items:
|
||
|
- const: fsl,imx8ulp-tpm
|
||
|
- const: fsl,imx7ulp-tpm
|
||
|
|
||
|
reg:
|
||
|
maxItems: 1
|
||
|
|
||
|
interrupts:
|
||
|
maxItems: 1
|
||
|
|
||
|
clocks:
|
||
|
items:
|
||
|
- description: SoC TPM ipg clock
|
||
|
- description: SoC TPM per clock
|
||
|
|
||
|
clock-names:
|
||
|
items:
|
||
|
- const: ipg
|
||
|
- const: per
|
||
|
|
||
|
required:
|
||
|
- compatible
|
||
|
- reg
|
||
|
- interrupts
|
||
|
- clocks
|
||
|
- clock-names
|
||
|
|
||
|
additionalProperties: false
|
||
|
|
||
|
examples:
|
||
|
- |
|
||
|
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||
|
|
||
|
timer@40260000 {
|
||
|
compatible = "fsl,imx7ulp-tpm";
|
||
|
reg = <0x40260000 0x1000>;
|
||
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||
|
<&pcc2 IMX7ULP_CLK_LPTPM5>;
|
||
|
clock-names = "ipg", "per";
|
||
|
};
|