108 lines
2.2 KiB
YAML
108 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mixel DSI PHY for i.MX8
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maintainers:
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- Guido Günther <agx@sigxcpu.org>
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description: |
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The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
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MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
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electrical signals for DSI.
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The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
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in either MIPI-DSI PHY mode or LVDS PHY mode.
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properties:
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compatible:
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enum:
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- fsl,imx8mq-mipi-dphy
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- fsl,imx8qxp-mipi-dphy
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: phy_ref
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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assigned-clock-rates:
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maxItems: 1
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"#phy-cells":
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const: 0
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fsl,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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A phandle which points to Control and Status Registers(CSR) module.
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#phy-cells"
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- power-domains
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8mq-mipi-dphy
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then:
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properties:
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fsl,syscon: false
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required:
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- assigned-clocks
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- assigned-clock-parents
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- assigned-clock-rates
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8qxp-mipi-dphy
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then:
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properties:
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assigned-clocks: false
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assigned-clock-parents: false
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assigned-clock-rates: false
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required:
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- fsl,syscon
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mq-clock.h>
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dphy: dphy@30a0030 {
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compatible = "fsl,imx8mq-mipi-dphy";
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reg = <0x30a00300 0x100>;
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clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
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clock-names = "phy_ref";
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assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
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assigned-clock-rates = <24000000>;
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#phy-cells = <0>;
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power-domains = <&pgc_mipi>;
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};
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