42 lines
1.6 KiB
Plaintext
42 lines
1.6 KiB
Plaintext
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Hisilicon Fast Ethernet MAC controller
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Required properties:
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- compatible: should contain one of the following version strings:
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* "hisilicon,hisi-femac-v1"
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* "hisilicon,hisi-femac-v2"
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and the soc string "hisilicon,hi3516cv300-femac".
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- reg: specifies base physical address(s) and size of the device registers.
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The first region is the MAC core register base and size.
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The second region is the global MAC control register.
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- interrupts: should contain the MAC interrupt.
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- clocks: A phandle to the MAC main clock.
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- resets: should contain the phandle to the MAC reset signal(required) and
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the PHY reset signal(optional).
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- reset-names: should contain the reset signal name "mac"(required)
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and "phy"(optional).
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- phy-mode: see ethernet.txt [1].
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- phy-handle: see ethernet.txt [1].
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- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
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The 1st cell is reset pre-delay in micro seconds.
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The 2nd cell is reset pulse in micro seconds.
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The 3rd cell is reset post-delay in micro seconds.
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The MAC address will be determined using the optional properties
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defined in ethernet.txt[1].
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[1] Documentation/devicetree/bindings/net/ethernet.txt
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Example:
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hisi_femac: ethernet@10090000 {
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compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
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reg = <0x10090000 0x1000>,<0x10091300 0x200>;
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interrupts = <12>;
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clocks = <&crg HI3518EV200_ETH_CLK>;
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resets = <&crg 0xec 0>,<&crg 0xec 3>;
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reset-names = "mac","phy";
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mac-address = [00 00 00 00 00 00];
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phy-mode = "mii";
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phy-handle = <&phy0>;
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hisilicon,phy-reset-delays-us = <10000 20000 20000>;
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};
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