307 lines
8.7 KiB
YAML
307 lines
8.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Atheros QCA83xx switch family
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maintainers:
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- John Crispin <john@phrozen.org>
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description:
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If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
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describing a port needs to have a valid phandle referencing the internal PHY
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it is connected to. This is because there is no N:N mapping of port and PHY
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ID. To declare the internal mdio-bus configuration, declare an MDIO node in
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the switch node and declare the phandle for the port, referencing the internal
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PHY it is connected to. In this config, an internal mdio-bus is registered and
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the MDIO master is used for communication. Mixed external and internal
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mdio-bus configurations are not supported by the hardware.
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properties:
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compatible:
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oneOf:
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- enum:
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- qca,qca8327
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- qca,qca8328
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- qca,qca8334
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- qca,qca8337
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description: |
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qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
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qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
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qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
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qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
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reg:
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maxItems: 1
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reset-gpios:
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description:
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GPIO to be used to reset the whole device
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maxItems: 1
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qca,ignore-power-on-sel:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Ignore power-on pin strapping to configure LED open-drain or EEPROM
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presence. This is needed for devices with incorrect configuration or when
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the OEM has decided not to use pin strapping and falls back to SW regs.
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qca,led-open-drain:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
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be set, otherwise the driver will fail at probe. This is required if the
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OEM does not use pin strapping to set this mode and prefers to set it
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using SW regs. The pin strappings related to LED open-drain mode are
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B68 on the QCA832x and B49 on the QCA833x.
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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description: Qca8k switch have an internal mdio to access switch port.
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If this is not present, the legacy mapping is used and the
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internal mdio access is used.
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With the legacy mapping the reg corresponding to the internal
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mdio is the switch reg with an offset of -1.
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patternProperties:
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"^(ethernet-)?ports$":
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^(ethernet-)?port@[0-6]$":
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type: object
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description: Ethernet switch ports
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$ref: dsa-port.yaml#
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properties:
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qca,sgmii-rxclk-falling-edge:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Set the receive clock phase to falling edge. Mostly commonly used on
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the QCA8327 with CPU port 0 set to SGMII.
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qca,sgmii-txclk-falling-edge:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Set the transmit clock phase to falling edge.
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qca,sgmii-enable-pll:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
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Signal Detection. On the QCA8327 this should not be enabled, otherwise
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the SGMII port will not initialize. When used on the QCA8337, revision 3
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or greater, a warning will be displayed. When the CPU port is set to
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SGMII on the QCA8337, it is advised to set this unless a communication
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issue is observed.
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unevaluatedProperties: false
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oneOf:
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- required:
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- ports
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- required:
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- ethernet-ports
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required:
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- compatible
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- reg
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additionalProperties: true
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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external_phy_port1: ethernet-phy@0 {
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reg = <0>;
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};
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external_phy_port2: ethernet-phy@1 {
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reg = <1>;
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};
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external_phy_port3: ethernet-phy@2 {
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reg = <2>;
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};
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external_phy_port4: ethernet-phy@3 {
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reg = <3>;
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};
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external_phy_port5: ethernet-phy@4 {
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reg = <4>;
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};
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switch@10 {
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compatible = "qca,qca8337";
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#address-cells = <1>;
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#size-cells = <0>;
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reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
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reg = <0x10>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ethernet = <&gmac1>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&external_phy_port1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&external_phy_port2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&external_phy_port3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&external_phy_port4>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-handle = <&external_phy_port5>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@10 {
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compatible = "qca,qca8337";
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#address-cells = <1>;
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#size-cells = <0>;
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reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
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reg = <0x10>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ethernet = <&gmac1>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&internal_phy_port1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&internal_phy_port2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&internal_phy_port3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&internal_phy_port4>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "internal";
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phy-handle = <&internal_phy_port5>;
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};
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port@6 {
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reg = <0>;
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ethernet = <&gmac1>;
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phy-mode = "sgmii";
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qca,sgmii-rxclk-falling-edge;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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internal_phy_port1: ethernet-phy@0 {
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reg = <0>;
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};
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internal_phy_port2: ethernet-phy@1 {
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reg = <1>;
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};
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internal_phy_port3: ethernet-phy@2 {
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reg = <2>;
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};
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internal_phy_port4: ethernet-phy@3 {
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reg = <3>;
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};
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internal_phy_port5: ethernet-phy@4 {
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reg = <4>;
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};
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};
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};
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};
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