259 lines
7.2 KiB
YAML
259 lines
7.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MTK MSDC Storage Host Controller Binding
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maintainers:
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- Chaotian Jing <chaotian.jing@mediatek.com>
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- Wenbin Mei <wenbin.mei@mediatek.com>
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allOf:
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- $ref: mmc-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-mmc
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- mediatek,mt2712-mmc
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- mediatek,mt6779-mmc
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- mediatek,mt6795-mmc
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- mediatek,mt7620-mmc
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- mediatek,mt7622-mmc
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- mediatek,mt8135-mmc
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- mediatek,mt8173-mmc
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- mediatek,mt8183-mmc
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- mediatek,mt8516-mmc
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- items:
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- const: mediatek,mt7623-mmc
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- const: mediatek,mt2701-mmc
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- items:
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- enum:
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- mediatek,mt8186-mmc
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- mediatek,mt8188-mmc
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- mediatek,mt8192-mmc
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- mediatek,mt8195-mmc
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- const: mediatek,mt8183-mmc
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reg:
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minItems: 1
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items:
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- description: base register (required).
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- description: top base register (required for MT8183).
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clocks:
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description:
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Should contain phandle for the clock feeding the MMC controller.
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minItems: 2
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items:
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- description: source clock (required).
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- description: HCLK which used for host (required).
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- description: independent source clock gate (required for MT2712).
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- description: bus clock used for internal register access (required for MT2712 MSDC0/3).
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- description: msdc subsys clock gate (required for MT8192).
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- description: peripheral bus clock gate (required for MT8192).
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- description: AXI bus clock gate (required for MT8192).
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- description: AHB bus clock gate (required for MT8192).
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clock-names:
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minItems: 2
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items:
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- const: source
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- const: hclk
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- const: source_cg
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- const: bus_clk
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- const: sys_cg
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- const: pclk_cg
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- const: axi_cg
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- const: ahb_cg
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interrupts:
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description:
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Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
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interrupt is required and be configured as wakeup source irq.
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minItems: 1
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maxItems: 2
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interrupt-names:
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items:
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- const: msdc
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- const: sdio_wakeup
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pinctrl-names:
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description:
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Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
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will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
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scenario.
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minItems: 2
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items:
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- const: default
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- const: state_uhs
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- const: state_eint
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pinctrl-0:
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description:
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should contain default/high speed pin ctrl.
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maxItems: 1
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pinctrl-1:
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description:
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should contain uhs mode pin ctrl.
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maxItems: 1
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pinctrl-2:
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description:
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should switch dat1 pin to GPIO mode.
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maxItems: 1
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assigned-clocks:
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description:
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PLL of the source clock.
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maxItems: 1
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assigned-clock-parents:
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description:
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parent of source clock, used for HS400 mode to get 400Mhz source clock.
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maxItems: 1
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hs400-ds-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HS400 DS delay setting.
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minimum: 0
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maximum: 0xffffffff
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mediatek,hs200-cmd-int-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HS200 command internal delay setting.
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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minimum: 0
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maximum: 31
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mediatek,hs400-cmd-int-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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HS400 command internal delay setting.
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This field has total 32 stages.
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The value is an integer from 0 to 31.
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minimum: 0
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maximum: 31
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mediatek,hs400-cmd-resp-sel-rising:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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HS400 command response sample selection.
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If present, HS400 command responses are sampled on rising edges.
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If not present, HS400 command responses are sampled on falling edges.
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mediatek,hs400-ds-dly3:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Gear of the third delay line for DS for input data latch in data
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pad macro, there are 32 stages from 0 to 31.
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For different corner IC, the time is different about one step, it is
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about 100ps.
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The value is confirmed by doing scan and calibration to find a best
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value with corner IC and it is valid only for HS400 mode.
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minimum: 0
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maximum: 31
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mediatek,latch-ck:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
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data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
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if not present, default value is 0.
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applied to compatible "mediatek,mt2701-mmc".
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minimum: 0
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maximum: 7
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resets:
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maxItems: 1
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reset-names:
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const: hrst
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- pinctrl-names
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- pinctrl-0
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- pinctrl-1
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- vmmc-supply
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- vqmmc-supply
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if:
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properties:
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compatible:
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contains:
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const: mediatek,mt8183-mmc
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then:
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properties:
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reg:
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minItems: 2
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8173-mmc";
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reg = <0x11230000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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vmmc-supply = <&mt6397_vemc_3v3_reg>;
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vqmmc-supply = <&mt6397_vio18_reg>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
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clock-names = "source", "hclk";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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hs400-ds-delay = <0x14015>;
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mediatek,hs200-cmd-int-delay = <26>;
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mediatek,hs400-cmd-int-delay = <14>;
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mediatek,hs400-cmd-resp-sel-rising;
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};
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mmc3: mmc@11260000 {
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compatible = "mediatek,mt8173-mmc";
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reg = <0x11260000 0x1000>;
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clock-names = "source", "hclk";
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clocks = <&pericfg CLK_PERI_MSDC30_3>,
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<&topckgen CLK_TOP_MSDC50_2_H_SEL>;
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interrupt-names = "msdc", "sdio_wakeup";
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interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
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<&pio 23 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default", "state_uhs", "state_eint";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_uhs>;
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pinctrl-2 = <&mmc2_pins_eint>;
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bus-width = <4>;
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max-frequency = <200000000>;
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cap-sd-highspeed;
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sd-uhs-sdr104;
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keep-power-in-suspend;
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wakeup-source;
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cap-sdio-irq;
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no-mmc;
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no-sd;
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non-removable;
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vmmc-supply = <&sdio_fixed_3v3>;
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vqmmc-supply = <&mt6397_vgp3_reg>;
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mmc-pwrseq = <&wifi_pwrseq>;
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};
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...
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