278 lines
7.8 KiB
YAML
278 lines
7.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Xenon SDHCI Controller
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description: |
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This file documents differences between the core MMC properties described by
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mmc-controller.yaml and the properties used by the Xenon implementation.
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Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
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Each SDHC is independent and owns independent resources, such as register
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sets, clock and PHY.
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Each SDHC should have an independent device tree node.
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maintainers:
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- Ulf Hansson <ulf.hansson@linaro.org>
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properties:
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compatible:
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oneOf:
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- enum:
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- marvell,armada-cp110-sdhci
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- marvell,armada-ap806-sdhci
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- items:
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- const: marvell,armada-ap807-sdhci
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- const: marvell,armada-ap806-sdhci
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- items:
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- const: marvell,armada-3700-sdhci
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- const: marvell,sdhci-xenon
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reg:
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minItems: 1
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maxItems: 2
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description: |
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For "marvell,armada-3700-sdhci", two register areas. The first one
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for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
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Voltage Control register. Please follow the examples with compatible
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"marvell,armada-3700-sdhci" in below.
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Please also check property marvell,pad-type in below.
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For other compatible strings, one register area for Xenon IP.
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: core
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- const: axi
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interrupts:
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maxItems: 1
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marvell,xenon-sdhc-id:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 7
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description: |
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Indicate the corresponding bit index of current SDHC in SDHC System
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Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
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enable/disable current SDHC.
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marvell,xenon-phy-type:
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- "emmc 5.1 phy"
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- "emmc 5.0 phy"
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description: |
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Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
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marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
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choice if this property is not provided. To select eMMC 5.0 PHY, set:
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marvell,xenon-phy-type = "emmc 5.0 phy"
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All those types of PHYs can support eMMC, SD and SDIO. Please note that
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this property only presents the type of PHY. It doesn't stand for the
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entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
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that this Xenon SDHC only supports eMMC 5.1.
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marvell,xenon-phy-znr:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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default: 0xf
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description: |
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Set PHY ZNR value.
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Only available for eMMC PHY.
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marvell,xenon-phy-zpr:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x1f
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default: 0xf
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description: |
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Set PHY ZPR value.
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Only available for eMMC PHY.
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marvell,xenon-phy-nr-success-tun:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 7
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default: 0x4
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description: |
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Set the number of required consecutive successful sampling points
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used to identify a valid sampling window, in tuning process.
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marvell,xenon-phy-tun-step-divider:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 64
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description: |
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Set the divider for calculating TUN_STEP.
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marvell,xenon-phy-slow-mode:
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type: boolean
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description: |
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If this property is selected, transfers will bypass PHY.
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Only available when bus frequency lower than 55MHz in SDR mode.
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Disabled by default. Please only try this property if timing issues
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always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
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SD Default Speed and HS mode and eMMC legacy speed mode.
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marvell,xenon-tun-count:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0x9
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description: |
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Xenon SDHC SoC usually doesn't provide re-tuning counter in
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Capabilities Register 3 Bit[11:8].
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This property provides the re-tuning counter.
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allOf:
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- $ref: mmc-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: marvell,armada-3700-sdhci
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then:
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properties:
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reg:
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items:
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- description: Xenon IP registers
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- description: Armada 3700 SoC PHY PAD Voltage Control register
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marvell,pad-type:
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$ref: /schemas/types.yaml#/definitions/string
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enum:
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- sd
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- fixed-1-8v
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description: |
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Type of Armada 3700 SoC PHY PAD Voltage Controller register.
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If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
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and is switched to 1.8V when later in higher speed mode.
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If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
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eMMC.
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Please follow the examples with compatible
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"marvell,armada-3700-sdhci" in below.
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required:
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- marvell,pad-type
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- if:
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properties:
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compatible:
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contains:
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enum:
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- marvell,armada-cp110-sdhci
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- marvell,armada-ap807-sdhci
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- marvell,armada-ap806-sdhci
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: core
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- const: axi
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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// For eMMC
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mmc@aa0000 {
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compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
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reg = <0xaa0000 0x1000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&emmc_clk 0>, <&axi_clk 0>;
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clock-names = "core", "axi";
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bus-width = <4>;
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marvell,xenon-phy-slow-mode;
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marvell,xenon-tun-count = <11>;
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non-removable;
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no-sd;
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no-sdio;
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/* Vmmc and Vqmmc are both fixed */
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};
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- |
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// For SD/SDIO
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mmc@ab0000 {
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compatible = "marvell,armada-cp110-sdhci";
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reg = <0xab0000 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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vqmmc-supply = <&sd_vqmmc_regulator>;
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vmmc-supply = <&sd_vmmc_regulator>;
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clocks = <&sdclk 0>, <&axi_clk 0>;
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clock-names = "core", "axi";
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bus-width = <4>;
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marvell,xenon-tun-count = <9>;
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};
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- |
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// For eMMC with compatible "marvell,armada-3700-sdhci":
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mmc@aa0000 {
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compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
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reg = <0xaa0000 0x1000>,
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<0x17808 0x4>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&emmcclk 0>;
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clock-names = "core";
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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non-removable;
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no-sd;
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no-sdio;
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/* Vmmc and Vqmmc are both fixed */
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marvell,pad-type = "fixed-1-8v";
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};
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- |
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// For SD/SDIO with compatible "marvell,armada-3700-sdhci":
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mmc@ab0000 {
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compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
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reg = <0xab0000 0x1000>,
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<0x17808 0x4>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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vqmmc-supply = <&sd_regulator>;
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/* Vmmc is fixed */
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clocks = <&sdclk 0>;
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clock-names = "core";
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bus-width = <4>;
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marvell,pad-type = "sd";
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};
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