198 lines
5.0 KiB
YAML
198 lines
5.0 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
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maintainers:
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- Inki Dae <inki.dae@samsung.com>
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- Seung-Woo Kim <sw0312.kim@samsung.com>
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- Kyungmin Park <kyungmin.park@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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properties:
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compatible:
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enum:
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- samsung,s3c2443-fimd
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- samsung,s3c6400-fimd
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- samsung,s5pv210-fimd
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- samsung,exynos3250-fimd
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- samsung,exynos4210-fimd
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- samsung,exynos5250-fimd
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- samsung,exynos5420-fimd
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'#address-cells':
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const: 1
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: sclk_fimd
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- const: fimd
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display-timings:
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$ref: ../panel/display-timings.yaml#
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i80-if-timings:
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type: object
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additionalProperties: false
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description: |
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Timing configuration for lcd i80 interface support.
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The parameters are defined as::
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VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
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: : : : :
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Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
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| cs-setup+1 | : : :
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|<---------->| : : :
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Chip Select ???????????????|____________:____________:____________|??
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| wr-setup+1 | | wr-hold+1 |
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|<---------->| |<---------->|
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Write Enable ????????????????????????????|____________|???????????????
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| wr-active+1|
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|<---------->|
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Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
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properties:
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cs-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of address signal is enabled until
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chip select is enabled.
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default: 0
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wr-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS is enabled.
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default: 1
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wr-hold:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS is disabled until write
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signal is disabled.
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default: 0
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wr-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS signal is enabled until
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write signal is enabled.
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default: 0
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iommus:
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minItems: 1
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maxItems: 2
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iommu-names:
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items:
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- const: m0
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- const: m1
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interrupts:
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items:
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- description: FIFO level
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- description: VSYNC
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- description: LCD system
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interrupt-names:
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items:
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- const: fifo
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- const: vsync
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- const: lcd_sys
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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samsung,invert-vden:
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type: boolean
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description:
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Video enable signal is inverted.
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samsung,invert-vclk:
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type: boolean
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description:
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Video clock signal is inverted.
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samsung,sysreg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to System Register syscon.
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'#size-cells':
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const: 0
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patternProperties:
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"^port@[0-4]+$":
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Contains ports with port with index::
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0 - for CAMIF0 input,
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1 - for CAMIF1 input,
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2 - for CAMIF2 input,
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3 - for parallel output,
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4 - for write-back interface
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos5420-fimd
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then:
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properties:
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iommus:
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minItems: 2
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maxItems: 2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos4.h>
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fimd@11c00000 {
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compatible = "samsung,exynos4210-fimd";
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interrupt-parent = <&combiner>;
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reg = <0x11c00000 0x20000>;
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interrupt-names = "fifo", "vsync", "lcd_sys";
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interrupts = <11 0>, <11 1>, <11 2>;
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clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
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clock-names = "sclk_fimd", "fimd";
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power-domains = <&pd_lcd0>;
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iommus = <&sysmmu_fimd0>;
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samsung,sysreg = <&sys_reg>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,invert-vden;
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samsung,invert-vclk;
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pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
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pinctrl-names = "default";
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port@3 {
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reg = <3>;
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fimd_dpi_ep: endpoint {
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remote-endpoint = <&lcd_ep>;
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};
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};
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};
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