146 lines
3.9 KiB
YAML
146 lines
3.9 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
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maintainers:
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- Inki Dae <inki.dae@samsung.com>
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- Seung-Woo Kim <sw0312.kim@samsung.com>
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- Kyungmin Park <kyungmin.park@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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DECON (Display and Enhancement Controller) is the Display Controller for the
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Exynos5433 series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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properties:
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compatible:
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enum:
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- samsung,exynos5433-decon
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- samsung,exynos5433-decon-tv
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clocks:
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maxItems: 11
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clock-names:
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items:
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- const: pclk
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- const: aclk_decon
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- const: aclk_smmu_decon0x
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- const: aclk_xiu_decon0x
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- const: pclk_smmu_decon0x
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- const: aclk_smmu_decon1x
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- const: aclk_xiu_decon1x
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- const: pclk_smmu_decon1x
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- const: sclk_decon_vclk
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- const: sclk_decon_eclk
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- const: dsd
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interrupts:
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minItems: 3
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maxItems: 4
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description: |
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Interrupts depend on mode of work:
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- video mode: vsync
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- command mode: lcd_sys
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- command mode with software trigger: lcd_sys, te
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interrupt-names:
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minItems: 3
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items:
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- const: fifo
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- const: vsync
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- const: lcd_sys
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- const: te
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iommus:
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maxItems: 2
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iommu-names:
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items:
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- const: m0
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- const: m1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Contains a port which is connected to mic node.
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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samsung,disp-sysreg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to DISP system controller interface.
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- ports
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5433.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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display-controller@13800000 {
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compatible = "samsung,exynos5433-decon";
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reg = <0x13800000 0x2104>;
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clocks = <&cmu_disp CLK_PCLK_DECON>,
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<&cmu_disp CLK_ACLK_DECON>,
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<&cmu_disp CLK_ACLK_SMMU_DECON0X>,
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<&cmu_disp CLK_ACLK_XIU_DECON0X>,
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<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
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<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
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<&cmu_disp CLK_ACLK_XIU_DECON1X>,
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<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
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<&cmu_disp CLK_SCLK_DECON_VCLK>,
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<&cmu_disp CLK_SCLK_DECON_ECLK>,
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<&cmu_disp CLK_SCLK_DSD>;
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clock-names = "pclk",
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"aclk_decon",
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"aclk_smmu_decon0x",
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"aclk_xiu_decon0x",
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"pclk_smmu_decon0x",
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"aclk_smmu_decon1x",
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"aclk_xiu_decon1x",
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"pclk_smmu_decon1x",
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"sclk_decon_vclk",
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"sclk_decon_eclk",
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"dsd";
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power-domains = <&pd_disp>;
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interrupt-names = "fifo", "vsync", "lcd_sys";
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interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
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samsung,disp-sysreg = <&syscon_disp>;
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iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
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iommu-names = "m0", "m1";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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decon_to_mic: endpoint {
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remote-endpoint = <&mic_to_decon>;
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};
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};
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};
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};
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