252 lines
5.9 KiB
YAML
252 lines
5.9 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only
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# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Devicetree bindings for the GMU attached to certain Adreno GPUs
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maintainers:
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- Rob Clark <robdclark@gmail.com>
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description: |
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These bindings describe the Graphics Management Unit (GMU) that is attached
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to members of the Adreno A6xx GPU family. The GMU provides on-device power
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management and support to improve power efficiency and reduce the load on
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the CPU.
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properties:
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compatible:
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items:
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- pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
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- const: qcom,adreno-gmu
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reg:
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minItems: 3
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maxItems: 4
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reg-names:
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minItems: 3
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maxItems: 4
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clocks:
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minItems: 4
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maxItems: 7
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clock-names:
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minItems: 4
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maxItems: 7
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interrupts:
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items:
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- description: GMU HFI interrupt
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- description: GMU interrupt
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interrupt-names:
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items:
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- const: hfi
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- const: gmu
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power-domains:
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items:
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- description: CX power domain
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- description: GX power domain
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power-domain-names:
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items:
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- const: cx
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- const: gx
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iommus:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- power-domains
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- power-domain-names
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- iommus
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- operating-points-v2
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,adreno-gmu-618.0
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- qcom,adreno-gmu-630.2
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then:
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properties:
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reg:
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items:
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- description: Core GMU registers
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- description: GMU PDC registers
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- description: GMU PDC sequence registers
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reg-names:
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items:
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- const: gmu
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- const: gmu_pdc
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- const: gmu_pdc_seq
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clocks:
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items:
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- description: GMU clock
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- description: GPU CX clock
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- description: GPU AXI clock
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- description: GPU MEMNOC clock
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clock-names:
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items:
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- const: gmu
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- const: cxo
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- const: axi
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- const: memnoc
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,adreno-gmu-635.0
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then:
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properties:
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reg:
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items:
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- description: Core GMU registers
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- description: Resource controller registers
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- description: GMU PDC registers
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reg-names:
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items:
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- const: gmu
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- const: rscc
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- const: gmu_pdc
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clocks:
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items:
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- description: GMU clock
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- description: GPU CX clock
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- description: GPU AXI clock
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- description: GPU MEMNOC clock
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- description: GPU AHB clock
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- description: GPU HUB CX clock
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- description: GPU SMMU vote clock
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clock-names:
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items:
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- const: gmu
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- const: cxo
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- const: axi
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- const: memnoc
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- const: ahb
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- const: hub
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- const: smmu_vote
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,adreno-gmu-640.1
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then:
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properties:
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reg:
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items:
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- description: Core GMU registers
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- description: GMU PDC registers
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- description: GMU PDC sequence registers
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reg-names:
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items:
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- const: gmu
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- const: gmu_pdc
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- const: gmu_pdc_seq
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,adreno-gmu-650.2
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then:
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properties:
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reg:
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items:
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- description: Core GMU registers
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- description: Resource controller registers
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- description: GMU PDC registers
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- description: GMU PDC sequence registers
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reg-names:
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items:
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- const: gmu
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- const: rscc
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- const: gmu_pdc
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- const: gmu_pdc_seq
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,adreno-gmu-640.1
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- qcom,adreno-gmu-650.2
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then:
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properties:
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clocks:
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items:
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- description: GPU AHB clock
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- description: GMU clock
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- description: GPU CX clock
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- description: GPU AXI clock
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- description: GPU MEMNOC clock
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clock-names:
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items:
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- const: ahb
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- const: gmu
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- const: cxo
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- const: axi
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- const: memnoc
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examples:
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- |
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gmu: gmu@506a000 {
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compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
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reg = <0x506a000 0x30000>,
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<0xb280000 0x10000>,
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<0xb480000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gmu", "cxo", "axi", "memnoc";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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power-domains = <&gpucc GPU_CX_GDSC>,
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<&gpucc GPU_GX_GDSC>;
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power-domain-names = "cx", "gx";
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iommus = <&adreno_smmu 5>;
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operating-points-v2 = <&gmu_opp_table>;
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};
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