145 lines
3.6 KiB
YAML
145 lines
3.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qm/qxp Display Pixel Link
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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description: |
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The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
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asynchronous linkage between pixel sources(display controller or
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camera module) and pixel consumers(imaging or displays).
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It consists of two distinct functions, a pixel transfer function and a
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control interface. Multiple pixel channels can exist per one control channel.
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This binding documentation is only for pixel links whose pixel sources are
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display controllers.
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The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
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firmware.
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properties:
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compatible:
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enum:
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- fsl,imx8qm-dc-pixel-link
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- fsl,imx8qxp-dc-pixel-link
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fsl,dc-id:
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$ref: /schemas/types.yaml#/definitions/uint8
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description: |
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u8 value representing the display controller index that the pixel link
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connects to.
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fsl,dc-stream-id:
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$ref: /schemas/types.yaml#/definitions/uint8
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description: |
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u8 value representing the display controller stream index that the pixel
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link connects to.
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enum: [0, 1]
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: The pixel link input port node from upstream video source.
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patternProperties:
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"^port@[1-4]$":
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$ref: /schemas/graph.yaml#/properties/port
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description: The pixel link output port node to downstream bridge.
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required:
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- port@0
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- port@1
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- port@2
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- port@3
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- port@4
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8qxp-dc-pixel-link
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then:
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properties:
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fsl,dc-id:
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const: 0
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx8qm-dc-pixel-link
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then:
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properties:
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fsl,dc-id:
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enum: [0, 1]
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required:
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- compatible
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- fsl,dc-id
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- fsl,dc-stream-id
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- ports
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additionalProperties: false
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examples:
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- |
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dc0-pixel-link0 {
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compatible = "fsl,imx8qxp-dc-pixel-link";
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fsl,dc-id = /bits/ 8 <0>;
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fsl,dc-stream-id = /bits/ 8 <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* from dc0 pixel combiner channel0 */
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port@0 {
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reg = <0>;
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dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
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remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
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};
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};
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/* to PXL2DPIs in MIPI/LVDS combo subsystems */
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
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};
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dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
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};
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};
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/* unused */
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port@2 {
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reg = <2>;
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};
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/* unused */
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port@3 {
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reg = <3>;
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};
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/* to imaging subsystem */
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port@4 {
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reg = <4>;
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};
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};
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};
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