95 lines
2.2 KiB
YAML
95 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arm CoreSight Trace Port Interface Unit
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maintainers:
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- Mathieu Poirier <mathieu.poirier@linaro.org>
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- Mike Leach <mike.leach@linaro.org>
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- Leo Yan <leo.yan@linaro.org>
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- Suzuki K Poulose <suzuki.poulose@arm.com>
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description: |
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CoreSight components are compliant with the ARM CoreSight architecture
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specification and can be connected in various topologies to suit a particular
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SoCs tracing needs. These trace components can generally be classified as
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sinks, links and sources. Trace data produced by one or more sources flows
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through the intermediate links connecting the source to the currently selected
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sink.
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The CoreSight Trace Port Interface Unit captures trace data from the trace bus
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and outputs it to an external trace port.
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# Need a custom select here or 'arm,primecell' will match on lots of nodes
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select:
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properties:
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compatible:
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contains:
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const: arm,coresight-tpiu
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required:
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- compatible
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allOf:
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- $ref: /schemas/arm/primecell.yaml#
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properties:
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compatible:
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items:
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- const: arm,coresight-tpiu
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- const: arm,primecell
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: apb_pclk
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- const: atclk
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power-domains:
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maxItems: 1
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in-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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additionalProperties: false
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properties:
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port:
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description: Input connection from the CoreSight Trace bus.
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$ref: /schemas/graph.yaml#/properties/port
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- in-ports
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unevaluatedProperties: false
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examples:
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- |
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tpiu@e3c05000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0xe3c05000 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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tpiu_in_port: endpoint {
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remote-endpoint = <&funnel4_out_port0>;
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};
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};
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};
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};
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...
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