314 lines
8.3 KiB
C
314 lines
8.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/* hypercalls: Check the ARM64's psuedo-firmware bitmap register interface.
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*
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* The test validates the basic hypercall functionalities that are exposed
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* via the psuedo-firmware bitmap register. This includes the registers'
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* read/write behavior before and after the VM has started, and if the
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* hypercalls are properly masked or unmasked to the guest when disabled or
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* enabled from the KVM userspace, respectively.
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*/
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#include <errno.h>
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#include <linux/arm-smccc.h>
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#include <asm/kvm.h>
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#include <kvm_util.h>
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#include "processor.h"
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#define FW_REG_ULIMIT_VAL(max_feat_bit) (GENMASK(max_feat_bit, 0))
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/* Last valid bits of the bitmapped firmware registers */
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#define KVM_REG_ARM_STD_BMAP_BIT_MAX 0
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#define KVM_REG_ARM_STD_HYP_BMAP_BIT_MAX 0
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#define KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_MAX 1
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struct kvm_fw_reg_info {
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uint64_t reg; /* Register definition */
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uint64_t max_feat_bit; /* Bit that represents the upper limit of the feature-map */
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};
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#define FW_REG_INFO(r) \
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{ \
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.reg = r, \
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.max_feat_bit = r##_BIT_MAX, \
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}
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static const struct kvm_fw_reg_info fw_reg_info[] = {
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FW_REG_INFO(KVM_REG_ARM_STD_BMAP),
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FW_REG_INFO(KVM_REG_ARM_STD_HYP_BMAP),
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FW_REG_INFO(KVM_REG_ARM_VENDOR_HYP_BMAP),
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};
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enum test_stage {
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TEST_STAGE_REG_IFACE,
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TEST_STAGE_HVC_IFACE_FEAT_DISABLED,
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TEST_STAGE_HVC_IFACE_FEAT_ENABLED,
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TEST_STAGE_HVC_IFACE_FALSE_INFO,
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TEST_STAGE_END,
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};
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static int stage = TEST_STAGE_REG_IFACE;
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struct test_hvc_info {
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uint32_t func_id;
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uint64_t arg1;
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};
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#define TEST_HVC_INFO(f, a1) \
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{ \
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.func_id = f, \
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.arg1 = a1, \
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}
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static const struct test_hvc_info hvc_info[] = {
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/* KVM_REG_ARM_STD_BMAP */
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TEST_HVC_INFO(ARM_SMCCC_TRNG_VERSION, 0),
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TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND64),
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TEST_HVC_INFO(ARM_SMCCC_TRNG_GET_UUID, 0),
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TEST_HVC_INFO(ARM_SMCCC_TRNG_RND32, 0),
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TEST_HVC_INFO(ARM_SMCCC_TRNG_RND64, 0),
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/* KVM_REG_ARM_STD_HYP_BMAP */
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TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_HV_PV_TIME_FEATURES),
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TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, ARM_SMCCC_HV_PV_TIME_ST),
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TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_ST, 0),
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/* KVM_REG_ARM_VENDOR_HYP_BMAP */
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TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID,
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ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID),
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TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID, 0),
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TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, KVM_PTP_VIRT_COUNTER),
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};
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/* Feed false hypercall info to test the KVM behavior */
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static const struct test_hvc_info false_hvc_info[] = {
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/* Feature support check against a different family of hypercalls */
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TEST_HVC_INFO(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID),
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TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_TRNG_RND64),
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TEST_HVC_INFO(ARM_SMCCC_HV_PV_TIME_FEATURES, ARM_SMCCC_TRNG_RND64),
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};
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static void guest_test_hvc(const struct test_hvc_info *hc_info)
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{
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unsigned int i;
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struct arm_smccc_res res;
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unsigned int hvc_info_arr_sz;
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hvc_info_arr_sz =
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hc_info == hvc_info ? ARRAY_SIZE(hvc_info) : ARRAY_SIZE(false_hvc_info);
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for (i = 0; i < hvc_info_arr_sz; i++, hc_info++) {
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memset(&res, 0, sizeof(res));
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smccc_hvc(hc_info->func_id, hc_info->arg1, 0, 0, 0, 0, 0, 0, &res);
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switch (stage) {
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case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
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case TEST_STAGE_HVC_IFACE_FALSE_INFO:
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GUEST_ASSERT_3(res.a0 == SMCCC_RET_NOT_SUPPORTED,
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res.a0, hc_info->func_id, hc_info->arg1);
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break;
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case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
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GUEST_ASSERT_3(res.a0 != SMCCC_RET_NOT_SUPPORTED,
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res.a0, hc_info->func_id, hc_info->arg1);
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break;
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default:
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GUEST_ASSERT_1(0, stage);
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}
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}
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}
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static void guest_code(void)
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{
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while (stage != TEST_STAGE_END) {
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switch (stage) {
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case TEST_STAGE_REG_IFACE:
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break;
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case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
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case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
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guest_test_hvc(hvc_info);
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break;
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case TEST_STAGE_HVC_IFACE_FALSE_INFO:
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guest_test_hvc(false_hvc_info);
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break;
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default:
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GUEST_ASSERT_1(0, stage);
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}
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GUEST_SYNC(stage);
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}
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GUEST_DONE();
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}
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struct st_time {
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uint32_t rev;
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uint32_t attr;
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uint64_t st_time;
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};
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#define STEAL_TIME_SIZE ((sizeof(struct st_time) + 63) & ~63)
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#define ST_GPA_BASE (1 << 30)
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static void steal_time_init(struct kvm_vcpu *vcpu)
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{
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uint64_t st_ipa = (ulong)ST_GPA_BASE;
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unsigned int gpages;
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gpages = vm_calc_num_guest_pages(VM_MODE_DEFAULT, STEAL_TIME_SIZE);
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vm_userspace_mem_region_add(vcpu->vm, VM_MEM_SRC_ANONYMOUS, ST_GPA_BASE, 1, gpages, 0);
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vcpu_device_attr_set(vcpu, KVM_ARM_VCPU_PVTIME_CTRL,
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KVM_ARM_VCPU_PVTIME_IPA, &st_ipa);
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}
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static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
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{
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uint64_t val;
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unsigned int i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) {
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const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
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/* First 'read' should be an upper limit of the features supported */
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vcpu_get_reg(vcpu, reg_info->reg, &val);
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TEST_ASSERT(val == FW_REG_ULIMIT_VAL(reg_info->max_feat_bit),
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"Expected all the features to be set for reg: 0x%lx; expected: 0x%lx; read: 0x%lx\n",
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reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), val);
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/* Test a 'write' by disabling all the features of the register map */
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ret = __vcpu_set_reg(vcpu, reg_info->reg, 0);
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TEST_ASSERT(ret == 0,
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"Failed to clear all the features of reg: 0x%lx; ret: %d\n",
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reg_info->reg, errno);
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vcpu_get_reg(vcpu, reg_info->reg, &val);
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TEST_ASSERT(val == 0,
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"Expected all the features to be cleared for reg: 0x%lx\n", reg_info->reg);
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/*
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* Test enabling a feature that's not supported.
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* Avoid this check if all the bits are occupied.
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*/
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if (reg_info->max_feat_bit < 63) {
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ret = __vcpu_set_reg(vcpu, reg_info->reg, BIT(reg_info->max_feat_bit + 1));
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TEST_ASSERT(ret != 0 && errno == EINVAL,
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"Unexpected behavior or return value (%d) while setting an unsupported feature for reg: 0x%lx\n",
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errno, reg_info->reg);
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}
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}
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}
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static void test_fw_regs_after_vm_start(struct kvm_vcpu *vcpu)
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{
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uint64_t val;
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unsigned int i;
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int ret;
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for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) {
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const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
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/*
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* Before starting the VM, the test clears all the bits.
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* Check if that's still the case.
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*/
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vcpu_get_reg(vcpu, reg_info->reg, &val);
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TEST_ASSERT(val == 0,
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"Expected all the features to be cleared for reg: 0x%lx\n",
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reg_info->reg);
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/*
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* Since the VM has run at least once, KVM shouldn't allow modification of
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* the registers and should return EBUSY. Set the registers and check for
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* the expected errno.
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*/
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ret = __vcpu_set_reg(vcpu, reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit));
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TEST_ASSERT(ret != 0 && errno == EBUSY,
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"Unexpected behavior or return value (%d) while setting a feature while VM is running for reg: 0x%lx\n",
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errno, reg_info->reg);
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}
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}
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static struct kvm_vm *test_vm_create(struct kvm_vcpu **vcpu)
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{
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struct kvm_vm *vm;
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vm = vm_create_with_one_vcpu(vcpu, guest_code);
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ucall_init(vm, NULL);
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steal_time_init(*vcpu);
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return vm;
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}
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static void test_guest_stage(struct kvm_vm **vm, struct kvm_vcpu **vcpu)
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{
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int prev_stage = stage;
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pr_debug("Stage: %d\n", prev_stage);
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/* Sync the stage early, the VM might be freed below. */
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stage++;
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sync_global_to_guest(*vm, stage);
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switch (prev_stage) {
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case TEST_STAGE_REG_IFACE:
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test_fw_regs_after_vm_start(*vcpu);
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break;
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case TEST_STAGE_HVC_IFACE_FEAT_DISABLED:
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/* Start a new VM so that all the features are now enabled by default */
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kvm_vm_free(*vm);
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*vm = test_vm_create(vcpu);
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break;
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case TEST_STAGE_HVC_IFACE_FEAT_ENABLED:
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case TEST_STAGE_HVC_IFACE_FALSE_INFO:
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break;
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default:
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TEST_FAIL("Unknown test stage: %d\n", prev_stage);
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}
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}
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static void test_run(void)
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{
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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struct ucall uc;
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bool guest_done = false;
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vm = test_vm_create(&vcpu);
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test_fw_regs_before_vm_start(vcpu);
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while (!guest_done) {
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vcpu_run(vcpu);
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switch (get_ucall(vcpu, &uc)) {
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case UCALL_SYNC:
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test_guest_stage(&vm, &vcpu);
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break;
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case UCALL_DONE:
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guest_done = true;
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break;
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case UCALL_ABORT:
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REPORT_GUEST_ASSERT_N(uc, "values: 0x%lx, 0x%lx; 0x%lx, stage: %u",
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GUEST_ASSERT_ARG(uc, 0),
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GUEST_ASSERT_ARG(uc, 1),
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GUEST_ASSERT_ARG(uc, 2), stage);
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break;
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default:
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TEST_FAIL("Unexpected guest exit\n");
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}
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}
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kvm_vm_free(vm);
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}
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int main(void)
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{
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setbuf(stdout, NULL);
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test_run();
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return 0;
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}
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