1332 lines
54 KiB
JSON
1332 lines
54 KiB
JSON
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[
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{
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"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"CounterMask": "2",
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"EventCode": "0xA3",
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"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"CounterMask": "6",
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"EventCode": "0xA3",
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"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
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"SampleAfterValue": "2000003",
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"UMask": "0x6"
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},
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{
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"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.ABORTED",
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"PEBS": "1",
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"PublicDescription": "Number of times HLE abort was triggered.",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.ABORTED_EVENTS",
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"SampleAfterValue": "2000003",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.ABORTED_MEM",
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"SampleAfterValue": "2000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
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"PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
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"SampleAfterValue": "2000003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.ABORTED_TIMER",
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"SampleAfterValue": "2000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
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"SampleAfterValue": "2000003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Number of times an HLE execution successfully committed",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.COMMIT",
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"PublicDescription": "Number of times HLE commit succeeded.",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of times an HLE execution started.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC8",
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"EventName": "HLE_RETIRED.START",
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"PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"Errata": "SKL089",
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"EventCode": "0xC3",
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"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
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"PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x80",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "1009",
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"TakenAlone": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x10",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "20011",
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"TakenAlone": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x100",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "503",
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"TakenAlone": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x20",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "100007",
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"TakenAlone": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x4",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "100003",
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"TakenAlone": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x200",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "101",
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"TakenAlone": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x40",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
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"SampleAfterValue": "2003",
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"TakenAlone": "1",
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||
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"Data_LA": "1",
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||
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"EventCode": "0xcd",
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||
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x8",
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"PEBS": "2",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
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||
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"SampleAfterValue": "50021",
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||
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"TakenAlone": "1",
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||
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"UMask": "0x1"
|
||
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},
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||
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{
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"BriefDescription": "Demand Data Read requests who miss L3 cache",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB0",
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"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
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"PublicDescription": "Demand Data Read requests who miss L3 cache.",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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||
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},
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{
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"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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||
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"CounterMask": "1",
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"EventCode": "0x60",
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"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
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"SampleAfterValue": "2000003",
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||
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"UMask": "0x10"
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||
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},
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||
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{
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||
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"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
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||
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"Counter": "0,1,2,3",
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||
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"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
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"EventCode": "0x60",
|
||
|
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"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
|
||
|
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"SampleAfterValue": "2000003",
|
||
|
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"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
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"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
|
||
|
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"Counter": "0,1,2,3",
|
||
|
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"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
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"CounterMask": "6",
|
||
|
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"EventCode": "0x60",
|
||
|
|
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
|
||
|
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"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
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"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000491",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00491",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00491",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00491",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000491",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800491",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch data reads that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000490",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00490",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00490",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00490",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000490",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800490",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch RFOs that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000120",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00120",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00120",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00120",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000120",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800120",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000122",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00122",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00122",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00122",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000122",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800122",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand code reads that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000004",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00004",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00004",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00004",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000004",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800004",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts demand data reads that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000001",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00001",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00001",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00001",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000001",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800001",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000002",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00002",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00002",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00002",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000002",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800002",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000400",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00400",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00400",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00400",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000400",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800400",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000010",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00010",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00010",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00010",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000010",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800010",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000020",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00020",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00020",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00020",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000020",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800020",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000080",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00080",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00080",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00080",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000080",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800080",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x3FBC000100",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x103FC00100",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x83FC00100",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63FC00100",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x604000100",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"MSRValue": "0x63B800100",
|
||
|
|
"Offcore": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.ABORTED",
|
||
|
|
"PEBS": "1",
|
||
|
|
"PublicDescription": "Number of times RTM abort was triggered.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
|
||
|
|
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x80"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.ABORTED_MEM",
|
||
|
|
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
|
||
|
|
"PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x40"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.ABORTED_TIMER",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
|
||
|
|
"PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x20"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution successfully committed",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.COMMIT",
|
||
|
|
"PublicDescription": "Number of times RTM commit succeeded.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an RTM execution started.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0xC9",
|
||
|
|
"EventName": "RTM_RETIRED.START",
|
||
|
|
"PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5d",
|
||
|
|
"EventName": "TX_EXEC.MISC1",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5d",
|
||
|
|
"EventName": "TX_EXEC.MISC2",
|
||
|
|
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5d",
|
||
|
|
"EventName": "TX_EXEC.MISC3",
|
||
|
|
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5d",
|
||
|
|
"EventName": "TX_EXEC.MISC4",
|
||
|
|
"PublicDescription": "RTM region detected inside HLE.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x5d",
|
||
|
|
"EventName": "TX_EXEC.MISC5",
|
||
|
|
"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.ABORT_CAPACITY",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x2"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.ABORT_CONFLICT",
|
||
|
|
"PublicDescription": "Number of times a TSX line had a cache conflict.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
|
||
|
|
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x10"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
|
||
|
|
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x8"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
|
||
|
|
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x20"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
|
||
|
|
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x4"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7",
|
||
|
|
"EventCode": "0x54",
|
||
|
|
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
|
||
|
|
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x40"
|
||
|
|
}
|
||
|
|
]
|