263 lines
9.2 KiB
JSON
263 lines
9.2 KiB
JSON
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[
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{
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"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x41",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x4f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of load ops retired.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x81",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of store ops retired.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "200003",
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"UMask": "0x82",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x80",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x10",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x100",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x20",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x4",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x200",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x40",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x8",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"TakenAlone": "1",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
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"CollectPEBSRecord": "3",
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"Counter": "0,1,2,3,4,5,6,7",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
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"PEBS": "2",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"UMask": "0x6",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "L2 code requests",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_CODE_RD",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "200003",
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"UMask": "0xe4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Demand Data Read access L2 cache",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "200003",
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"UMask": "0xe1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "100003",
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"UMask": "0x41",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "100003",
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"UMask": "0x4f",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Retired load instructions.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_LOADS",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "1000003",
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"UMask": "0x81",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Retired store instructions.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_STORES",
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"L1_Hit_Indication": "1",
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"PEBS": "1",
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"PEBScounters": "0,1,2,3",
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"SampleAfterValue": "1000003",
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"UMask": "0x82",
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"Unit": "cpu_core"
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}
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]
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