492 lines
13 KiB
C
492 lines
13 KiB
C
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
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*/
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#include <linux/module.h>
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#include <sound/sof.h>
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#include <sound/sof/xtensa.h>
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#include <sound/soc-acpi.h>
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#include <sound/soc-acpi-intel-match.h>
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#include <sound/intel-dsp-config.h>
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#include "../ops.h"
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#include "atom.h"
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#include "shim.h"
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#include "../sof-acpi-dev.h"
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#include "../sof-audio.h"
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#include "../../intel/common/soc-intel-quirks.h"
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static const struct snd_sof_debugfs_map byt_debugfs[] = {
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{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
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SOF_DEBUGFS_ACCESS_D0_ONLY},
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{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
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SOF_DEBUGFS_ACCESS_D0_ONLY},
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{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static const struct snd_sof_debugfs_map cht_debugfs[] = {
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{"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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{"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
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SOF_DEBUGFS_ACCESS_D0_ONLY},
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{"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
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SOF_DEBUGFS_ACCESS_D0_ONLY},
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{"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
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SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
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{
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/* Disable Interrupt from both sides */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);
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/* Put DSP into reset, set reset vector */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
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SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
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SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
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}
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static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
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{
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byt_reset_dsp_disable_int(sdev);
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return 0;
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}
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static int byt_resume(struct snd_sof_dev *sdev)
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{
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/* enable BUSY and disable DONE Interrupt by default */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
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SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
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SHIM_IMRX_DONE);
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return 0;
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}
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static int byt_remove(struct snd_sof_dev *sdev)
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{
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byt_reset_dsp_disable_int(sdev);
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return 0;
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}
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static int byt_acpi_probe(struct snd_sof_dev *sdev)
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{
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struct snd_sof_pdata *pdata = sdev->pdata;
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const struct sof_dev_desc *desc = pdata->desc;
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struct platform_device *pdev =
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container_of(sdev->dev, struct platform_device, dev);
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const struct sof_intel_dsp_desc *chip;
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struct resource *mmio;
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u32 base, size;
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int ret;
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chip = get_chip_info(sdev->pdata);
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if (!chip) {
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dev_err(sdev->dev, "error: no such device supported\n");
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return -EIO;
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}
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sdev->num_cores = chip->cores_num;
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/* DSP DMA can only access low 31 bits of host memory */
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ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
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return ret;
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}
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/* LPE base */
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mmio = platform_get_resource(pdev, IORESOURCE_MEM,
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desc->resindex_lpe_base);
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if (mmio) {
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base = mmio->start;
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size = resource_size(mmio);
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} else {
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dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
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desc->resindex_lpe_base);
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return -EINVAL;
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}
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dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
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sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
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if (!sdev->bar[DSP_BAR]) {
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dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
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base, size);
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return -ENODEV;
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}
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dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
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/* TODO: add offsets */
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sdev->mmio_bar = DSP_BAR;
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sdev->mailbox_bar = DSP_BAR;
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/* IMR base - optional */
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if (desc->resindex_imr_base == -1)
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goto irq;
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mmio = platform_get_resource(pdev, IORESOURCE_MEM,
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desc->resindex_imr_base);
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if (mmio) {
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base = mmio->start;
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size = resource_size(mmio);
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} else {
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dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
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desc->resindex_imr_base);
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return -ENODEV;
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}
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/* some BIOSes don't map IMR */
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if (base == 0x55aa55aa || base == 0x0) {
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dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
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goto irq;
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}
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dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
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sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
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if (!sdev->bar[IMR_BAR]) {
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dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
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base, size);
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return -ENODEV;
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}
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dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
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irq:
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/* register our IRQ */
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sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
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if (sdev->ipc_irq < 0)
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return sdev->ipc_irq;
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dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
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ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
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atom_irq_handler, atom_irq_thread,
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IRQF_SHARED, "AudioDSP", sdev);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to register IRQ %d\n",
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sdev->ipc_irq);
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return ret;
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}
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/* enable BUSY and disable DONE Interrupt by default */
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snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
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SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
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SHIM_IMRX_DONE);
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/* set default mailbox offset for FW ready message */
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sdev->dsp_box.offset = MBOX_OFFSET;
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return ret;
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}
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/* baytrail ops */
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static struct snd_sof_dsp_ops sof_byt_ops = {
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/* device init */
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.probe = byt_acpi_probe,
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.remove = byt_remove,
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/* DSP core boot / reset */
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.run = atom_run,
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.reset = atom_reset,
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/* Register IO */
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.write = sof_io_write,
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.read = sof_io_read,
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.write64 = sof_io_write64,
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.read64 = sof_io_read64,
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/* Block IO */
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.block_read = sof_block_read,
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.block_write = sof_block_write,
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/* Mailbox IO */
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.mailbox_read = sof_mailbox_read,
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.mailbox_write = sof_mailbox_write,
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/* doorbell */
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.irq_handler = atom_irq_handler,
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.irq_thread = atom_irq_thread,
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/* ipc */
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.send_msg = atom_send_msg,
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.get_mailbox_offset = atom_get_mailbox_offset,
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.get_window_offset = atom_get_window_offset,
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.ipc_msg_data = sof_ipc_msg_data,
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.set_stream_data_offset = sof_set_stream_data_offset,
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/* machine driver */
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.machine_select = atom_machine_select,
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.machine_register = sof_machine_register,
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.machine_unregister = sof_machine_unregister,
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.set_mach_params = atom_set_mach_params,
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/* debug */
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.debug_map = byt_debugfs,
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.debug_map_count = ARRAY_SIZE(byt_debugfs),
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.dbg_dump = atom_dump,
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.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
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/* stream callbacks */
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.pcm_open = sof_stream_pcm_open,
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.pcm_close = sof_stream_pcm_close,
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/*Firmware loading */
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.load_firmware = snd_sof_load_firmware_memcpy,
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/* PM */
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.suspend = byt_suspend,
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.resume = byt_resume,
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/* DAI drivers */
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.drv = atom_dai,
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.num_drv = 3, /* we have only 3 SSPs on byt*/
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/* ALSA HW info flags */
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.hw_info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_BATCH,
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.dsp_arch_ops = &sof_xtensa_arch_ops,
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};
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static const struct sof_intel_dsp_desc byt_chip_info = {
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.cores_num = 1,
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.host_managed_cores_mask = 1,
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.hw_ip_version = SOF_INTEL_BAYTRAIL,
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};
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/* cherrytrail and braswell ops */
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static struct snd_sof_dsp_ops sof_cht_ops = {
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/* device init */
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.probe = byt_acpi_probe,
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.remove = byt_remove,
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/* DSP core boot / reset */
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.run = atom_run,
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.reset = atom_reset,
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/* Register IO */
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.write = sof_io_write,
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.read = sof_io_read,
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.write64 = sof_io_write64,
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.read64 = sof_io_read64,
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/* Block IO */
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.block_read = sof_block_read,
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.block_write = sof_block_write,
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/* Mailbox IO */
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.mailbox_read = sof_mailbox_read,
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.mailbox_write = sof_mailbox_write,
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/* doorbell */
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.irq_handler = atom_irq_handler,
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.irq_thread = atom_irq_thread,
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/* ipc */
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.send_msg = atom_send_msg,
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.get_mailbox_offset = atom_get_mailbox_offset,
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.get_window_offset = atom_get_window_offset,
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.ipc_msg_data = sof_ipc_msg_data,
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.set_stream_data_offset = sof_set_stream_data_offset,
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/* machine driver */
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.machine_select = atom_machine_select,
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.machine_register = sof_machine_register,
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.machine_unregister = sof_machine_unregister,
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.set_mach_params = atom_set_mach_params,
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/* debug */
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.debug_map = cht_debugfs,
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.debug_map_count = ARRAY_SIZE(cht_debugfs),
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.dbg_dump = atom_dump,
|
||
|
|
.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
|
||
|
|
|
||
|
|
/* stream callbacks */
|
||
|
|
.pcm_open = sof_stream_pcm_open,
|
||
|
|
.pcm_close = sof_stream_pcm_close,
|
||
|
|
|
||
|
|
/*Firmware loading */
|
||
|
|
.load_firmware = snd_sof_load_firmware_memcpy,
|
||
|
|
|
||
|
|
/* PM */
|
||
|
|
.suspend = byt_suspend,
|
||
|
|
.resume = byt_resume,
|
||
|
|
|
||
|
|
/* DAI drivers */
|
||
|
|
.drv = atom_dai,
|
||
|
|
/* all 6 SSPs may be available for cherrytrail */
|
||
|
|
.num_drv = 6,
|
||
|
|
|
||
|
|
/* ALSA HW info flags */
|
||
|
|
.hw_info = SNDRV_PCM_INFO_MMAP |
|
||
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
||
|
|
SNDRV_PCM_INFO_INTERLEAVED |
|
||
|
|
SNDRV_PCM_INFO_PAUSE |
|
||
|
|
SNDRV_PCM_INFO_BATCH,
|
||
|
|
|
||
|
|
.dsp_arch_ops = &sof_xtensa_arch_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct sof_intel_dsp_desc cht_chip_info = {
|
||
|
|
.cores_num = 1,
|
||
|
|
.host_managed_cores_mask = 1,
|
||
|
|
.hw_ip_version = SOF_INTEL_BAYTRAIL,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* BYTCR uses different IRQ index */
|
||
|
|
static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
|
||
|
|
.machines = snd_soc_acpi_intel_baytrail_machines,
|
||
|
|
.resindex_lpe_base = 0,
|
||
|
|
.resindex_pcicfg_base = 1,
|
||
|
|
.resindex_imr_base = 2,
|
||
|
|
.irqindex_host_ipc = 0,
|
||
|
|
.chip_info = &byt_chip_info,
|
||
|
|
.ipc_supported_mask = BIT(SOF_IPC),
|
||
|
|
.ipc_default = SOF_IPC,
|
||
|
|
.default_fw_path = {
|
||
|
|
[SOF_IPC] = "intel/sof",
|
||
|
|
},
|
||
|
|
.default_tplg_path = {
|
||
|
|
[SOF_IPC] = "intel/sof-tplg",
|
||
|
|
},
|
||
|
|
.default_fw_filename = {
|
||
|
|
[SOF_IPC] = "sof-byt.ri",
|
||
|
|
},
|
||
|
|
.nocodec_tplg_filename = "sof-byt-nocodec.tplg",
|
||
|
|
.ops = &sof_byt_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct sof_dev_desc sof_acpi_baytrail_desc = {
|
||
|
|
.machines = snd_soc_acpi_intel_baytrail_machines,
|
||
|
|
.resindex_lpe_base = 0,
|
||
|
|
.resindex_pcicfg_base = 1,
|
||
|
|
.resindex_imr_base = 2,
|
||
|
|
.irqindex_host_ipc = 5,
|
||
|
|
.chip_info = &byt_chip_info,
|
||
|
|
.ipc_supported_mask = BIT(SOF_IPC),
|
||
|
|
.ipc_default = SOF_IPC,
|
||
|
|
.default_fw_path = {
|
||
|
|
[SOF_IPC] = "intel/sof",
|
||
|
|
},
|
||
|
|
.default_tplg_path = {
|
||
|
|
[SOF_IPC] = "intel/sof-tplg",
|
||
|
|
},
|
||
|
|
.default_fw_filename = {
|
||
|
|
[SOF_IPC] = "sof-byt.ri",
|
||
|
|
},
|
||
|
|
.nocodec_tplg_filename = "sof-byt-nocodec.tplg",
|
||
|
|
.ops = &sof_byt_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
|
||
|
|
.machines = snd_soc_acpi_intel_cherrytrail_machines,
|
||
|
|
.resindex_lpe_base = 0,
|
||
|
|
.resindex_pcicfg_base = 1,
|
||
|
|
.resindex_imr_base = 2,
|
||
|
|
.irqindex_host_ipc = 5,
|
||
|
|
.chip_info = &cht_chip_info,
|
||
|
|
.ipc_supported_mask = BIT(SOF_IPC),
|
||
|
|
.ipc_default = SOF_IPC,
|
||
|
|
.default_fw_path = {
|
||
|
|
[SOF_IPC] = "intel/sof",
|
||
|
|
},
|
||
|
|
.default_tplg_path = {
|
||
|
|
[SOF_IPC] = "intel/sof-tplg",
|
||
|
|
},
|
||
|
|
.default_fw_filename = {
|
||
|
|
[SOF_IPC] = "sof-cht.ri",
|
||
|
|
},
|
||
|
|
.nocodec_tplg_filename = "sof-cht-nocodec.tplg",
|
||
|
|
.ops = &sof_cht_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct acpi_device_id sof_baytrail_match[] = {
|
||
|
|
{ "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
|
||
|
|
{ "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(acpi, sof_baytrail_match);
|
||
|
|
|
||
|
|
static int sof_baytrail_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
const struct sof_dev_desc *desc;
|
||
|
|
const struct acpi_device_id *id;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
id = acpi_match_device(dev->driver->acpi_match_table, dev);
|
||
|
|
if (!id)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
|
||
|
|
if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
|
||
|
|
dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
desc = (const struct sof_dev_desc *)id->driver_data;
|
||
|
|
if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev))
|
||
|
|
desc = &sof_acpi_baytrailcr_desc;
|
||
|
|
|
||
|
|
return sof_acpi_probe(pdev, desc);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* acpi_driver definition */
|
||
|
|
static struct platform_driver snd_sof_acpi_intel_byt_driver = {
|
||
|
|
.probe = sof_baytrail_probe,
|
||
|
|
.remove = sof_acpi_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "sof-audio-acpi-intel-byt",
|
||
|
|
.pm = &sof_acpi_pm,
|
||
|
|
.acpi_match_table = sof_baytrail_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(snd_sof_acpi_intel_byt_driver);
|
||
|
|
|
||
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
||
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
|
||
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
||
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
|
||
|
|
MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);
|