83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 Hisilicon Limited.
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*/
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#ifndef __DTS_HIX5HD2_CLOCK_H
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#define __DTS_HIX5HD2_CLOCK_H
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/* fixed rate */
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#define HIX5HD2_FIXED_1200M 1
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#define HIX5HD2_FIXED_400M 2
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#define HIX5HD2_FIXED_48M 3
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#define HIX5HD2_FIXED_24M 4
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#define HIX5HD2_FIXED_600M 5
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#define HIX5HD2_FIXED_300M 6
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#define HIX5HD2_FIXED_75M 7
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#define HIX5HD2_FIXED_200M 8
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#define HIX5HD2_FIXED_100M 9
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#define HIX5HD2_FIXED_40M 10
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#define HIX5HD2_FIXED_150M 11
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#define HIX5HD2_FIXED_1728M 12
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#define HIX5HD2_FIXED_28P8M 13
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#define HIX5HD2_FIXED_432M 14
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#define HIX5HD2_FIXED_345P6M 15
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#define HIX5HD2_FIXED_288M 16
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#define HIX5HD2_FIXED_60M 17
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#define HIX5HD2_FIXED_750M 18
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#define HIX5HD2_FIXED_500M 19
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#define HIX5HD2_FIXED_54M 20
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#define HIX5HD2_FIXED_27M 21
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#define HIX5HD2_FIXED_1500M 22
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#define HIX5HD2_FIXED_375M 23
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#define HIX5HD2_FIXED_187M 24
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#define HIX5HD2_FIXED_250M 25
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#define HIX5HD2_FIXED_125M 26
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#define HIX5HD2_FIXED_2P02M 27
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#define HIX5HD2_FIXED_50M 28
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#define HIX5HD2_FIXED_25M 29
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#define HIX5HD2_FIXED_83M 30
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/* mux clocks */
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#define HIX5HD2_SFC_MUX 64
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#define HIX5HD2_MMC_MUX 65
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#define HIX5HD2_FEPHY_MUX 66
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#define HIX5HD2_SD_MUX 67
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/* gate clocks */
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#define HIX5HD2_SFC_RST 128
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#define HIX5HD2_SFC_CLK 129
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#define HIX5HD2_MMC_CIU_CLK 130
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#define HIX5HD2_MMC_BIU_CLK 131
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#define HIX5HD2_MMC_CIU_RST 132
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#define HIX5HD2_FWD_BUS_CLK 133
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#define HIX5HD2_FWD_SYS_CLK 134
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#define HIX5HD2_MAC0_PHY_CLK 135
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#define HIX5HD2_SD_CIU_CLK 136
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#define HIX5HD2_SD_BIU_CLK 137
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#define HIX5HD2_SD_CIU_RST 138
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#define HIX5HD2_WDG0_CLK 139
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#define HIX5HD2_WDG0_RST 140
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#define HIX5HD2_I2C0_CLK 141
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#define HIX5HD2_I2C0_RST 142
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#define HIX5HD2_I2C1_CLK 143
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#define HIX5HD2_I2C1_RST 144
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#define HIX5HD2_I2C2_CLK 145
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#define HIX5HD2_I2C2_RST 146
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#define HIX5HD2_I2C3_CLK 147
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#define HIX5HD2_I2C3_RST 148
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#define HIX5HD2_I2C4_CLK 149
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#define HIX5HD2_I2C4_RST 150
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#define HIX5HD2_I2C5_CLK 151
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#define HIX5HD2_I2C5_RST 152
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/* complex */
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#define HIX5HD2_MAC0_CLK 192
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#define HIX5HD2_MAC1_CLK 193
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#define HIX5HD2_SATA_CLK 194
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#define HIX5HD2_USB_CLK 195
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#define HIX5HD2_NR_CLKS 256
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#endif /* __DTS_HIX5HD2_CLOCK_H */
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