308 lines
9.0 KiB
C
308 lines
9.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/* Synopsys DesignWare 8250 library. */
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/math.h>
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#include <linux/property.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_core.h>
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#include "8250_dwlib.h"
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
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#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
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#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
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#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
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#define DW_UART_RAR 0xc4 /* Receive Address Register */
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#define DW_UART_TAR 0xc8 /* Transmit Address Register */
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#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
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#define DW_UART_CPR 0xf4 /* Component Parameter Register */
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#define DW_UART_UCV 0xf8 /* UART Component Version */
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/* Receive / Transmit Address Register bits */
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#define DW_UART_ADDR_MASK GENMASK(7, 0)
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/* Line Status Register bits */
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#define DW_UART_LSR_ADDR_RCVD BIT(8)
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/* Transceiver Control Register bits */
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#define DW_UART_TCR_RS485_EN BIT(0)
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#define DW_UART_TCR_RE_POL BIT(1)
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#define DW_UART_TCR_DE_POL BIT(2)
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#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
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#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
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#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
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#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
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/* Line Extended Control Register bits */
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#define DW_UART_LCR_EXT_DLS_E BIT(0)
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#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
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#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
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#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
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/* Component Parameter Register bits */
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#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
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#define DW_UART_CPR_AFCE_MODE BIT(4)
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#define DW_UART_CPR_THRE_MODE BIT(5)
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#define DW_UART_CPR_SIR_MODE BIT(6)
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#define DW_UART_CPR_SIR_LP_MODE BIT(7)
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#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
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#define DW_UART_CPR_FIFO_ACCESS BIT(9)
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#define DW_UART_CPR_FIFO_STAT BIT(10)
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#define DW_UART_CPR_SHADOW BIT(11)
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#define DW_UART_CPR_ENCODED_PARMS BIT(12)
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#define DW_UART_CPR_DMA_EXTRA BIT(13)
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#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
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/* Helper for FIFO size calculation */
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#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
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/*
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* divisor = div(I) + div(F)
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* "I" means integer, "F" means fractional
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* quot = div(I) = clk / (16 * baud)
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* frac = div(F) * 2^dlf_size
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*
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* let rem = clk % (16 * baud)
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* we have: div(F) * (16 * baud) = rem
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* so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
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*/
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static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud,
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unsigned int *frac)
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{
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unsigned int quot, rem, base_baud = baud * 16;
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struct dw8250_port_data *d = p->private_data;
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quot = p->uartclk / base_baud;
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rem = p->uartclk % base_baud;
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*frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
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return quot;
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}
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static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
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unsigned int quot, unsigned int quot_frac)
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{
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dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
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serial8250_do_set_divisor(p, baud, quot, quot_frac);
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}
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void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios,
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const struct ktermios *old)
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{
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p->status &= ~UPSTAT_AUTOCTS;
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if (termios->c_cflag & CRTSCTS)
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p->status |= UPSTAT_AUTOCTS;
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serial8250_do_set_termios(p, termios, old);
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/* Filter addresses which have 9th bit set */
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p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD;
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p->read_status_mask |= DW_UART_LSR_ADDR_RCVD;
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}
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EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
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/*
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* Wait until re is de-asserted for sure. An ongoing receive will keep
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* re asserted until end of frame. Without BUSY indication available,
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* only available course of action is to wait for the time it takes to
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* receive one frame (there might nothing to receive but w/o BUSY the
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* driver cannot know).
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*/
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static void dw8250_wait_re_deassert(struct uart_port *p)
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{
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ndelay(p->frame_time);
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}
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static void dw8250_update_rar(struct uart_port *p, u32 addr)
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{
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u32 re_en = dw8250_readl_ext(p, DW_UART_RE_EN);
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/*
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* RAR shouldn't be changed while receiving. Thus, de-assert RE_EN
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* if asserted and wait.
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*/
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if (re_en)
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dw8250_writel_ext(p, DW_UART_RE_EN, 0);
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dw8250_wait_re_deassert(p);
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dw8250_writel_ext(p, DW_UART_RAR, addr);
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if (re_en)
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dw8250_writel_ext(p, DW_UART_RE_EN, re_en);
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}
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static void dw8250_rs485_set_addr(struct uart_port *p, struct serial_rs485 *rs485,
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struct ktermios *termios)
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{
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u32 lcr = dw8250_readl_ext(p, DW_UART_LCR_EXT);
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if (rs485->flags & SER_RS485_ADDRB) {
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lcr |= DW_UART_LCR_EXT_DLS_E;
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if (termios)
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termios->c_cflag |= ADDRB;
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if (rs485->flags & SER_RS485_ADDR_RECV) {
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u32 delta = p->rs485.flags ^ rs485->flags;
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/*
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* rs485 (param) is equal to uart_port's rs485 only during init
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* (during init, delta is not yet applicable).
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*/
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if (unlikely(&p->rs485 == rs485))
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delta = rs485->flags;
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if ((delta & SER_RS485_ADDR_RECV) ||
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(p->rs485.addr_recv != rs485->addr_recv))
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dw8250_update_rar(p, rs485->addr_recv);
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lcr |= DW_UART_LCR_EXT_ADDR_MATCH;
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} else {
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lcr &= ~DW_UART_LCR_EXT_ADDR_MATCH;
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}
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if (rs485->flags & SER_RS485_ADDR_DEST) {
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/*
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* Don't skip writes here as another endpoint could
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* have changed communication line's destination
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* address in between.
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*/
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dw8250_writel_ext(p, DW_UART_TAR, rs485->addr_dest);
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lcr |= DW_UART_LCR_EXT_SEND_ADDR;
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}
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} else {
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lcr = 0;
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}
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dw8250_writel_ext(p, DW_UART_LCR_EXT, lcr);
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}
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static int dw8250_rs485_config(struct uart_port *p, struct ktermios *termios,
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struct serial_rs485 *rs485)
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{
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u32 tcr;
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tcr = dw8250_readl_ext(p, DW_UART_TCR);
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tcr &= ~DW_UART_TCR_XFER_MODE;
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if (rs485->flags & SER_RS485_ENABLED) {
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tcr |= DW_UART_TCR_RS485_EN;
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if (rs485->flags & SER_RS485_RX_DURING_TX)
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tcr |= DW_UART_TCR_XFER_MODE_DE_DURING_RE;
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else
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tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE;
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dw8250_writel_ext(p, DW_UART_DE_EN, 1);
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dw8250_writel_ext(p, DW_UART_RE_EN, 1);
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} else {
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if (termios)
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termios->c_cflag &= ~ADDRB;
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tcr &= ~DW_UART_TCR_RS485_EN;
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}
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/* Reset to default polarity */
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tcr |= DW_UART_TCR_DE_POL;
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tcr &= ~DW_UART_TCR_RE_POL;
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if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
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tcr &= ~DW_UART_TCR_DE_POL;
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if (device_property_read_bool(p->dev, "rs485-rx-active-high"))
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tcr |= DW_UART_TCR_RE_POL;
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dw8250_writel_ext(p, DW_UART_TCR, tcr);
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/* Addressing mode can only be set up after TCR */
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if (rs485->flags & SER_RS485_ENABLED)
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dw8250_rs485_set_addr(p, rs485, termios);
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return 0;
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}
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/*
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* Tests if RE_EN register can have non-zero value to see if RS-485 HW support
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* is present.
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*/
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static bool dw8250_detect_rs485_hw(struct uart_port *p)
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{
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u32 reg;
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dw8250_writel_ext(p, DW_UART_RE_EN, 1);
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reg = dw8250_readl_ext(p, DW_UART_RE_EN);
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dw8250_writel_ext(p, DW_UART_RE_EN, 0);
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return reg;
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}
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static const struct serial_rs485 dw8250_rs485_supported = {
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.flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_RTS_ON_SEND |
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SER_RS485_RTS_AFTER_SEND | SER_RS485_ADDRB | SER_RS485_ADDR_RECV |
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SER_RS485_ADDR_DEST,
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};
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void dw8250_setup_port(struct uart_port *p)
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{
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struct dw8250_port_data *pd = p->private_data;
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struct dw8250_data *data = to_dw8250_data(pd);
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struct uart_8250_port *up = up_to_u8250p(p);
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u32 reg, old_dlf;
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pd->hw_rs485_support = dw8250_detect_rs485_hw(p);
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if (pd->hw_rs485_support) {
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p->rs485_config = dw8250_rs485_config;
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up->lsr_save_mask = LSR_SAVE_FLAGS | DW_UART_LSR_ADDR_RCVD;
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p->rs485_supported = dw8250_rs485_supported;
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} else {
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p->rs485_config = serial8250_em485_config;
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p->rs485_supported = serial8250_em485_supported;
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up->rs485_start_tx = serial8250_em485_start_tx;
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up->rs485_stop_tx = serial8250_em485_stop_tx;
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}
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up->capabilities |= UART_CAP_NOTEMT;
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/*
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* If the Component Version Register returns zero, we know that
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* ADDITIONAL_FEATURES are not enabled. No need to go any further.
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*/
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reg = dw8250_readl_ext(p, DW_UART_UCV);
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if (!reg)
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return;
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dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
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(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
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/* Preserve value written by firmware or bootloader */
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old_dlf = dw8250_readl_ext(p, DW_UART_DLF);
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dw8250_writel_ext(p, DW_UART_DLF, ~0U);
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reg = dw8250_readl_ext(p, DW_UART_DLF);
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dw8250_writel_ext(p, DW_UART_DLF, old_dlf);
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if (reg) {
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pd->dlf_size = fls(reg);
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p->get_divisor = dw8250_get_divisor;
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p->set_divisor = dw8250_set_divisor;
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}
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reg = dw8250_readl_ext(p, DW_UART_CPR);
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if (!reg) {
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reg = data->pdata->cpr_val;
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dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
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}
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if (!reg)
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return;
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/* Select the type based on FIFO */
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if (reg & DW_UART_CPR_FIFO_MODE) {
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p->type = PORT_16550A;
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p->flags |= UPF_FIXED_TYPE;
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p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
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up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT;
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}
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if (reg & DW_UART_CPR_AFCE_MODE)
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up->capabilities |= UART_CAP_AFE;
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if (reg & DW_UART_CPR_SIR_MODE)
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up->capabilities |= UART_CAP_IRDA;
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}
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EXPORT_SYMBOL_GPL(dw8250_setup_port);
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