220 lines
7.0 KiB
C
220 lines
7.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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#include "soctherm.h"
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#define TEGRA132_THERMTRIP_ANY_EN_MASK (0x1 << 28)
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#define TEGRA132_THERMTRIP_MEM_EN_MASK (0x1 << 27)
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#define TEGRA132_THERMTRIP_GPU_EN_MASK (0x1 << 26)
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#define TEGRA132_THERMTRIP_CPU_EN_MASK (0x1 << 25)
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#define TEGRA132_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
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#define TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
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#define TEGRA132_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
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#define TEGRA132_THERMTRIP_TSENSE_THRESH_MASK 0xff
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#define TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
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#define TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
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#define TEGRA132_THRESH_GRAIN 1000
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#define TEGRA132_BPTT 8
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static const struct tegra_tsensor_configuration tegra132_tsensor_config = {
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.tall = 16300,
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.tiddq_en = 1,
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.ten_count = 1,
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.tsample = 120,
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.tsample_ate = 480,
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};
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static const struct tegra_tsensor_group tegra132_tsensor_group_cpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_CPU,
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.name = "cpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_CPU_MASK,
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.pllx_hotspot_diff = 10,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
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.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA132_THERMTRIP_CPU_EN_MASK,
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.thermtrip_threshold_mask = TEGRA132_THERMTRIP_CPU_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_CPU_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
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.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group tegra132_tsensor_group_gpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_GPU,
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.name = "gpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_GPU_MASK,
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.pllx_hotspot_diff = 5,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
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.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA132_THERMTRIP_GPU_EN_MASK,
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.thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_GPU_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
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.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group tegra132_tsensor_group_pll = {
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.id = TEGRA124_SOCTHERM_SENSOR_PLLX,
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.name = "pll",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
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.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA132_THERMTRIP_TSENSE_EN_MASK,
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.thermtrip_threshold_mask = TEGRA132_THERMTRIP_TSENSE_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
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.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group tegra132_tsensor_group_mem = {
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.id = TEGRA124_SOCTHERM_SENSOR_MEM,
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.name = "mem",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_MEM_MASK,
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.pllx_hotspot_diff = 0,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
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.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA132_THERMTRIP_MEM_EN_MASK,
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.thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_MEM_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
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.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group *tegra132_tsensor_groups[] = {
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&tegra132_tsensor_group_cpu,
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&tegra132_tsensor_group_gpu,
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&tegra132_tsensor_group_pll,
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&tegra132_tsensor_group_mem,
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};
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static struct tegra_tsensor tegra132_tsensors[] = {
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{
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.name = "cpu0",
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.base = 0xc0,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x098,
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.fuse_corr_alpha = 1126600,
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.fuse_corr_beta = -9433500,
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.group = &tegra132_tsensor_group_cpu,
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}, {
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.name = "cpu1",
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.base = 0xe0,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x084,
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.fuse_corr_alpha = 1110800,
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.fuse_corr_beta = -7383000,
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.group = &tegra132_tsensor_group_cpu,
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}, {
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.name = "cpu2",
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.base = 0x100,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x088,
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.fuse_corr_alpha = 1113800,
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.fuse_corr_beta = -6215200,
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.group = &tegra132_tsensor_group_cpu,
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}, {
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.name = "cpu3",
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.base = 0x120,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x12c,
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.fuse_corr_alpha = 1129600,
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.fuse_corr_beta = -8196100,
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.group = &tegra132_tsensor_group_cpu,
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}, {
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.name = "mem0",
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.base = 0x140,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x158,
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.fuse_corr_alpha = 1132900,
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.fuse_corr_beta = -6755300,
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.group = &tegra132_tsensor_group_mem,
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}, {
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.name = "mem1",
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.base = 0x160,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x15c,
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.fuse_corr_alpha = 1142300,
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.fuse_corr_beta = -7374200,
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.group = &tegra132_tsensor_group_mem,
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}, {
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.name = "gpu",
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.base = 0x180,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x154,
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.fuse_corr_alpha = 1125100,
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.fuse_corr_beta = -6350400,
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.group = &tegra132_tsensor_group_gpu,
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}, {
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.name = "pllx",
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.base = 0x1a0,
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.config = &tegra132_tsensor_config,
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.calib_fuse_offset = 0x160,
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.fuse_corr_alpha = 1118100,
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.fuse_corr_beta = -8208800,
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.group = &tegra132_tsensor_group_pll,
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},
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};
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/*
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* Mask/shift bits in FUSE_TSENSOR_COMMON and
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* FUSE_TSENSOR_COMMON, which are described in
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* tegra_soctherm_fuse.c
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*/
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static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
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.fuse_base_cp_mask = 0x3ff,
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.fuse_base_cp_shift = 0,
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.fuse_base_ft_mask = 0x7ff << 10,
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.fuse_base_ft_shift = 10,
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.fuse_shift_ft_mask = 0x1f << 21,
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.fuse_shift_ft_shift = 21,
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.fuse_spare_realignment = 0x1fc,
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};
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const struct tegra_soctherm_soc tegra132_soctherm = {
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.tsensors = tegra132_tsensors,
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.num_tsensors = ARRAY_SIZE(tegra132_tsensors),
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.ttgs = tegra132_tsensor_groups,
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.num_ttgs = ARRAY_SIZE(tegra132_tsensor_groups),
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.tfuse = &tegra132_soctherm_fuse,
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.thresh_grain = TEGRA132_THRESH_GRAIN,
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.bptt = TEGRA132_BPTT,
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.use_ccroc = true,
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};
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