349 lines
9.4 KiB
C
349 lines
9.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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//
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// VF610 pinctrl driver based on imx pinmux and pinconf core
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//
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// Copyright 2013 Freescale Semiconductor, Inc.
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum vf610_pads {
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VF610_PAD_PTA6 = 0,
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VF610_PAD_PTA8 = 1,
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VF610_PAD_PTA9 = 2,
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VF610_PAD_PTA10 = 3,
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VF610_PAD_PTA11 = 4,
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VF610_PAD_PTA12 = 5,
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VF610_PAD_PTA16 = 6,
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VF610_PAD_PTA17 = 7,
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VF610_PAD_PTA18 = 8,
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VF610_PAD_PTA19 = 9,
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VF610_PAD_PTA20 = 10,
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VF610_PAD_PTA21 = 11,
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VF610_PAD_PTA22 = 12,
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VF610_PAD_PTA23 = 13,
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VF610_PAD_PTA24 = 14,
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VF610_PAD_PTA25 = 15,
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VF610_PAD_PTA26 = 16,
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VF610_PAD_PTA27 = 17,
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VF610_PAD_PTA28 = 18,
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VF610_PAD_PTA29 = 19,
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VF610_PAD_PTA30 = 20,
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VF610_PAD_PTA31 = 21,
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VF610_PAD_PTB0 = 22,
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VF610_PAD_PTB1 = 23,
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VF610_PAD_PTB2 = 24,
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VF610_PAD_PTB3 = 25,
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VF610_PAD_PTB4 = 26,
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VF610_PAD_PTB5 = 27,
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VF610_PAD_PTB6 = 28,
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VF610_PAD_PTB7 = 29,
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VF610_PAD_PTB8 = 30,
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VF610_PAD_PTB9 = 31,
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VF610_PAD_PTB10 = 32,
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VF610_PAD_PTB11 = 33,
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VF610_PAD_PTB12 = 34,
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VF610_PAD_PTB13 = 35,
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VF610_PAD_PTB14 = 36,
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VF610_PAD_PTB15 = 37,
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VF610_PAD_PTB16 = 38,
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VF610_PAD_PTB17 = 39,
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VF610_PAD_PTB18 = 40,
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VF610_PAD_PTB19 = 41,
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VF610_PAD_PTB20 = 42,
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VF610_PAD_PTB21 = 43,
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VF610_PAD_PTB22 = 44,
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VF610_PAD_PTC0 = 45,
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VF610_PAD_PTC1 = 46,
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VF610_PAD_PTC2 = 47,
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VF610_PAD_PTC3 = 48,
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VF610_PAD_PTC4 = 49,
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VF610_PAD_PTC5 = 50,
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VF610_PAD_PTC6 = 51,
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VF610_PAD_PTC7 = 52,
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VF610_PAD_PTC8 = 53,
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VF610_PAD_PTC9 = 54,
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VF610_PAD_PTC10 = 55,
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VF610_PAD_PTC11 = 56,
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VF610_PAD_PTC12 = 57,
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VF610_PAD_PTC13 = 58,
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VF610_PAD_PTC14 = 59,
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VF610_PAD_PTC15 = 60,
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VF610_PAD_PTC16 = 61,
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VF610_PAD_PTC17 = 62,
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VF610_PAD_PTD31 = 63,
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VF610_PAD_PTD30 = 64,
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VF610_PAD_PTD29 = 65,
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VF610_PAD_PTD28 = 66,
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VF610_PAD_PTD27 = 67,
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VF610_PAD_PTD26 = 68,
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VF610_PAD_PTD25 = 69,
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VF610_PAD_PTD24 = 70,
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VF610_PAD_PTD23 = 71,
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VF610_PAD_PTD22 = 72,
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VF610_PAD_PTD21 = 73,
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VF610_PAD_PTD20 = 74,
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VF610_PAD_PTD19 = 75,
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VF610_PAD_PTD18 = 76,
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VF610_PAD_PTD17 = 77,
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VF610_PAD_PTD16 = 78,
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VF610_PAD_PTD0 = 79,
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VF610_PAD_PTD1 = 80,
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VF610_PAD_PTD2 = 81,
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VF610_PAD_PTD3 = 82,
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VF610_PAD_PTD4 = 83,
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VF610_PAD_PTD5 = 84,
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VF610_PAD_PTD6 = 85,
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VF610_PAD_PTD7 = 86,
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VF610_PAD_PTD8 = 87,
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VF610_PAD_PTD9 = 88,
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VF610_PAD_PTD10 = 89,
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VF610_PAD_PTD11 = 90,
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VF610_PAD_PTD12 = 91,
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VF610_PAD_PTD13 = 92,
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VF610_PAD_PTB23 = 93,
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VF610_PAD_PTB24 = 94,
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VF610_PAD_PTB25 = 95,
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VF610_PAD_PTB26 = 96,
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VF610_PAD_PTB27 = 97,
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VF610_PAD_PTB28 = 98,
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VF610_PAD_PTC26 = 99,
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VF610_PAD_PTC27 = 100,
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VF610_PAD_PTC28 = 101,
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VF610_PAD_PTC29 = 102,
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VF610_PAD_PTC30 = 103,
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VF610_PAD_PTC31 = 104,
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VF610_PAD_PTE0 = 105,
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VF610_PAD_PTE1 = 106,
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VF610_PAD_PTE2 = 107,
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VF610_PAD_PTE3 = 108,
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VF610_PAD_PTE4 = 109,
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VF610_PAD_PTE5 = 110,
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VF610_PAD_PTE6 = 111,
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VF610_PAD_PTE7 = 112,
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VF610_PAD_PTE8 = 113,
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VF610_PAD_PTE9 = 114,
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VF610_PAD_PTE10 = 115,
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VF610_PAD_PTE11 = 116,
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VF610_PAD_PTE12 = 117,
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VF610_PAD_PTE13 = 118,
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VF610_PAD_PTE14 = 119,
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VF610_PAD_PTE15 = 120,
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VF610_PAD_PTE16 = 121,
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VF610_PAD_PTE17 = 122,
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VF610_PAD_PTE18 = 123,
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VF610_PAD_PTE19 = 124,
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VF610_PAD_PTE20 = 125,
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VF610_PAD_PTE21 = 126,
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VF610_PAD_PTE22 = 127,
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VF610_PAD_PTE23 = 128,
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VF610_PAD_PTE24 = 129,
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VF610_PAD_PTE25 = 130,
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VF610_PAD_PTE26 = 131,
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VF610_PAD_PTE27 = 132,
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VF610_PAD_PTE28 = 133,
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VF610_PAD_PTA7 = 134,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(VF610_PAD_PTA6),
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IMX_PINCTRL_PIN(VF610_PAD_PTA8),
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IMX_PINCTRL_PIN(VF610_PAD_PTA9),
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IMX_PINCTRL_PIN(VF610_PAD_PTA10),
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IMX_PINCTRL_PIN(VF610_PAD_PTA11),
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IMX_PINCTRL_PIN(VF610_PAD_PTA12),
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IMX_PINCTRL_PIN(VF610_PAD_PTA16),
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IMX_PINCTRL_PIN(VF610_PAD_PTA17),
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IMX_PINCTRL_PIN(VF610_PAD_PTA18),
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IMX_PINCTRL_PIN(VF610_PAD_PTA19),
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IMX_PINCTRL_PIN(VF610_PAD_PTA20),
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IMX_PINCTRL_PIN(VF610_PAD_PTA21),
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IMX_PINCTRL_PIN(VF610_PAD_PTA22),
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IMX_PINCTRL_PIN(VF610_PAD_PTA23),
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IMX_PINCTRL_PIN(VF610_PAD_PTA24),
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IMX_PINCTRL_PIN(VF610_PAD_PTA25),
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IMX_PINCTRL_PIN(VF610_PAD_PTA26),
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IMX_PINCTRL_PIN(VF610_PAD_PTA27),
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IMX_PINCTRL_PIN(VF610_PAD_PTA28),
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IMX_PINCTRL_PIN(VF610_PAD_PTA29),
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IMX_PINCTRL_PIN(VF610_PAD_PTA30),
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IMX_PINCTRL_PIN(VF610_PAD_PTA31),
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IMX_PINCTRL_PIN(VF610_PAD_PTB0),
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IMX_PINCTRL_PIN(VF610_PAD_PTB1),
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IMX_PINCTRL_PIN(VF610_PAD_PTB2),
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IMX_PINCTRL_PIN(VF610_PAD_PTB3),
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IMX_PINCTRL_PIN(VF610_PAD_PTB4),
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IMX_PINCTRL_PIN(VF610_PAD_PTB5),
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IMX_PINCTRL_PIN(VF610_PAD_PTB6),
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IMX_PINCTRL_PIN(VF610_PAD_PTB7),
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IMX_PINCTRL_PIN(VF610_PAD_PTB8),
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IMX_PINCTRL_PIN(VF610_PAD_PTB9),
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IMX_PINCTRL_PIN(VF610_PAD_PTB10),
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IMX_PINCTRL_PIN(VF610_PAD_PTB11),
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IMX_PINCTRL_PIN(VF610_PAD_PTB12),
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IMX_PINCTRL_PIN(VF610_PAD_PTB13),
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IMX_PINCTRL_PIN(VF610_PAD_PTB14),
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IMX_PINCTRL_PIN(VF610_PAD_PTB15),
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IMX_PINCTRL_PIN(VF610_PAD_PTB16),
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IMX_PINCTRL_PIN(VF610_PAD_PTB17),
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IMX_PINCTRL_PIN(VF610_PAD_PTB18),
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IMX_PINCTRL_PIN(VF610_PAD_PTB19),
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IMX_PINCTRL_PIN(VF610_PAD_PTB20),
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IMX_PINCTRL_PIN(VF610_PAD_PTB21),
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IMX_PINCTRL_PIN(VF610_PAD_PTB22),
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IMX_PINCTRL_PIN(VF610_PAD_PTC0),
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IMX_PINCTRL_PIN(VF610_PAD_PTC1),
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IMX_PINCTRL_PIN(VF610_PAD_PTC2),
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IMX_PINCTRL_PIN(VF610_PAD_PTC3),
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IMX_PINCTRL_PIN(VF610_PAD_PTC4),
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IMX_PINCTRL_PIN(VF610_PAD_PTC5),
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IMX_PINCTRL_PIN(VF610_PAD_PTC6),
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IMX_PINCTRL_PIN(VF610_PAD_PTC7),
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IMX_PINCTRL_PIN(VF610_PAD_PTC8),
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IMX_PINCTRL_PIN(VF610_PAD_PTC9),
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IMX_PINCTRL_PIN(VF610_PAD_PTC10),
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IMX_PINCTRL_PIN(VF610_PAD_PTC11),
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IMX_PINCTRL_PIN(VF610_PAD_PTC12),
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IMX_PINCTRL_PIN(VF610_PAD_PTC13),
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IMX_PINCTRL_PIN(VF610_PAD_PTC14),
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IMX_PINCTRL_PIN(VF610_PAD_PTC15),
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IMX_PINCTRL_PIN(VF610_PAD_PTC16),
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IMX_PINCTRL_PIN(VF610_PAD_PTC17),
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IMX_PINCTRL_PIN(VF610_PAD_PTD31),
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IMX_PINCTRL_PIN(VF610_PAD_PTD30),
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IMX_PINCTRL_PIN(VF610_PAD_PTD29),
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IMX_PINCTRL_PIN(VF610_PAD_PTD28),
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IMX_PINCTRL_PIN(VF610_PAD_PTD27),
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IMX_PINCTRL_PIN(VF610_PAD_PTD26),
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IMX_PINCTRL_PIN(VF610_PAD_PTD25),
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IMX_PINCTRL_PIN(VF610_PAD_PTD24),
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IMX_PINCTRL_PIN(VF610_PAD_PTD23),
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IMX_PINCTRL_PIN(VF610_PAD_PTD22),
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IMX_PINCTRL_PIN(VF610_PAD_PTD21),
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IMX_PINCTRL_PIN(VF610_PAD_PTD20),
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IMX_PINCTRL_PIN(VF610_PAD_PTD19),
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IMX_PINCTRL_PIN(VF610_PAD_PTD18),
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IMX_PINCTRL_PIN(VF610_PAD_PTD17),
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IMX_PINCTRL_PIN(VF610_PAD_PTD16),
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IMX_PINCTRL_PIN(VF610_PAD_PTD0),
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IMX_PINCTRL_PIN(VF610_PAD_PTD1),
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IMX_PINCTRL_PIN(VF610_PAD_PTD2),
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IMX_PINCTRL_PIN(VF610_PAD_PTD3),
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IMX_PINCTRL_PIN(VF610_PAD_PTD4),
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IMX_PINCTRL_PIN(VF610_PAD_PTD5),
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IMX_PINCTRL_PIN(VF610_PAD_PTD6),
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IMX_PINCTRL_PIN(VF610_PAD_PTD7),
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IMX_PINCTRL_PIN(VF610_PAD_PTD8),
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IMX_PINCTRL_PIN(VF610_PAD_PTD9),
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IMX_PINCTRL_PIN(VF610_PAD_PTD10),
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IMX_PINCTRL_PIN(VF610_PAD_PTD11),
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IMX_PINCTRL_PIN(VF610_PAD_PTD12),
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IMX_PINCTRL_PIN(VF610_PAD_PTD13),
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IMX_PINCTRL_PIN(VF610_PAD_PTB23),
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IMX_PINCTRL_PIN(VF610_PAD_PTB24),
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IMX_PINCTRL_PIN(VF610_PAD_PTB25),
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IMX_PINCTRL_PIN(VF610_PAD_PTB26),
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IMX_PINCTRL_PIN(VF610_PAD_PTB27),
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IMX_PINCTRL_PIN(VF610_PAD_PTB28),
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IMX_PINCTRL_PIN(VF610_PAD_PTC26),
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IMX_PINCTRL_PIN(VF610_PAD_PTC27),
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IMX_PINCTRL_PIN(VF610_PAD_PTC28),
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IMX_PINCTRL_PIN(VF610_PAD_PTC29),
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IMX_PINCTRL_PIN(VF610_PAD_PTC30),
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IMX_PINCTRL_PIN(VF610_PAD_PTC31),
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IMX_PINCTRL_PIN(VF610_PAD_PTE0),
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IMX_PINCTRL_PIN(VF610_PAD_PTE1),
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IMX_PINCTRL_PIN(VF610_PAD_PTE2),
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IMX_PINCTRL_PIN(VF610_PAD_PTE3),
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IMX_PINCTRL_PIN(VF610_PAD_PTE4),
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IMX_PINCTRL_PIN(VF610_PAD_PTE5),
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IMX_PINCTRL_PIN(VF610_PAD_PTE6),
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IMX_PINCTRL_PIN(VF610_PAD_PTE7),
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IMX_PINCTRL_PIN(VF610_PAD_PTE8),
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IMX_PINCTRL_PIN(VF610_PAD_PTE9),
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IMX_PINCTRL_PIN(VF610_PAD_PTE10),
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IMX_PINCTRL_PIN(VF610_PAD_PTE11),
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IMX_PINCTRL_PIN(VF610_PAD_PTE12),
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IMX_PINCTRL_PIN(VF610_PAD_PTE13),
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IMX_PINCTRL_PIN(VF610_PAD_PTE14),
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IMX_PINCTRL_PIN(VF610_PAD_PTE15),
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IMX_PINCTRL_PIN(VF610_PAD_PTE16),
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IMX_PINCTRL_PIN(VF610_PAD_PTE17),
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IMX_PINCTRL_PIN(VF610_PAD_PTE18),
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IMX_PINCTRL_PIN(VF610_PAD_PTE19),
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IMX_PINCTRL_PIN(VF610_PAD_PTE20),
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IMX_PINCTRL_PIN(VF610_PAD_PTE21),
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IMX_PINCTRL_PIN(VF610_PAD_PTE22),
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IMX_PINCTRL_PIN(VF610_PAD_PTE23),
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IMX_PINCTRL_PIN(VF610_PAD_PTE24),
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IMX_PINCTRL_PIN(VF610_PAD_PTE25),
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IMX_PINCTRL_PIN(VF610_PAD_PTE26),
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IMX_PINCTRL_PIN(VF610_PAD_PTE27),
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IMX_PINCTRL_PIN(VF610_PAD_PTE28),
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IMX_PINCTRL_PIN(VF610_PAD_PTA7),
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};
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static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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|
const struct imx_pin_reg *pin_reg;
|
||
|
|
u32 reg;
|
||
|
|
|
||
|
|
pin_reg = &ipctl->pin_regs[offset];
|
||
|
|
if (pin_reg->mux_reg == -1)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
/* IBE always enabled allows us to read the value "on the wire" */
|
||
|
|
reg = readl(ipctl->base + pin_reg->mux_reg);
|
||
|
|
if (input)
|
||
|
|
reg &= ~0x2;
|
||
|
|
else
|
||
|
|
reg |= 0x2;
|
||
|
|
writel(reg, ipctl->base + pin_reg->mux_reg);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct imx_pinctrl_soc_info vf610_pinctrl_info = {
|
||
|
|
.pins = vf610_pinctrl_pads,
|
||
|
|
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
|
||
|
|
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
|
||
|
|
.gpio_set_direction = vf610_pmx_gpio_set_direction,
|
||
|
|
.mux_mask = 0x700000,
|
||
|
|
.mux_shift = 20,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id vf610_pinctrl_of_match[] = {
|
||
|
|
{ .compatible = "fsl,vf610-iomuxc", },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
|
||
|
|
static int vf610_pinctrl_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver vf610_pinctrl_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "vf610-pinctrl",
|
||
|
|
.of_match_table = vf610_pinctrl_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
.probe = vf610_pinctrl_probe,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init vf610_pinctrl_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&vf610_pinctrl_driver);
|
||
|
|
}
|
||
|
|
arch_initcall(vf610_pinctrl_init);
|