417 lines
10 KiB
C
417 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Loongson Extend I/O Interrupt Controller support
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#define pr_fmt(fmt) "eiointc: " fmt
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#define EIOINTC_REG_NODEMAP 0x14a0
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#define EIOINTC_REG_IPMAP 0x14c0
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#define EIOINTC_REG_ENABLE 0x1600
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#define EIOINTC_REG_BOUNCE 0x1680
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#define EIOINTC_REG_ISR 0x1800
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#define EIOINTC_REG_ROUTE 0x1c00
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#define VEC_REG_COUNT 4
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#define VEC_COUNT_PER_REG 64
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#define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG)
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#define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
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#define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
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#define EIOINTC_ALL_ENABLE 0xffffffff
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#define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE)
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static int nr_pics;
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struct eiointc_priv {
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u32 node;
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nodemask_t node_map;
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cpumask_t cpuspan_map;
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struct fwnode_handle *domain_handle;
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struct irq_domain *eiointc_domain;
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};
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static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
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static void eiointc_enable(void)
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{
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uint64_t misc;
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misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
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misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
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iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
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}
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static int cpu_to_eio_node(int cpu)
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{
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return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
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}
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static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
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{
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int i, node, cpu_node, route_node;
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unsigned char coremap;
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uint32_t pos_off, data, data_byte, data_mask;
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pos_off = pos & ~3;
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data_byte = pos & 3;
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data_mask = ~BIT_MASK(data_byte) & 0xf;
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/* Calculate node and coremap of target irq */
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cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
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coremap = BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
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for_each_online_cpu(i) {
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node = cpu_to_eio_node(i);
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if (!node_isset(node, *node_map))
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continue;
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/* EIO node 0 is in charge of inter-node interrupt dispatch */
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route_node = (node == mnode) ? cpu_node : node;
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data = ((coremap | (route_node << 4)) << (data_byte * 8));
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csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
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}
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}
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static DEFINE_RAW_SPINLOCK(affinity_lock);
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static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
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{
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unsigned int cpu;
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unsigned long flags;
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uint32_t vector, regaddr;
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struct cpumask intersect_affinity;
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struct eiointc_priv *priv = d->domain->host_data;
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raw_spin_lock_irqsave(&affinity_lock, flags);
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cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
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cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
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if (cpumask_empty(&intersect_affinity)) {
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raw_spin_unlock_irqrestore(&affinity_lock, flags);
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return -EINVAL;
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}
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cpu = cpumask_first(&intersect_affinity);
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vector = d->hwirq;
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regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
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/* Mask target vector */
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csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)),
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0x0, priv->node * CORES_PER_EIO_NODE);
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/* Set route for target vector */
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eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
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/* Unmask target vector */
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csr_any_send(regaddr, EIOINTC_ALL_ENABLE,
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0x0, priv->node * CORES_PER_EIO_NODE);
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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raw_spin_unlock_irqrestore(&affinity_lock, flags);
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return IRQ_SET_MASK_OK;
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}
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static int eiointc_index(int node)
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{
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int i;
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for (i = 0; i < nr_pics; i++) {
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if (node_isset(node, eiointc_priv[i]->node_map))
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return i;
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}
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return -1;
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}
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static int eiointc_router_init(unsigned int cpu)
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{
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int i, bit;
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uint32_t data;
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uint32_t node = cpu_to_eio_node(cpu);
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int index = eiointc_index(node);
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if (index < 0) {
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pr_err("Error: invalid nodemap!\n");
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return -1;
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}
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if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
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eiointc_enable();
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for (i = 0; i < VEC_COUNT / 32; i++) {
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data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
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iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
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}
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for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
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bit = BIT(1 + index); /* Route to IP[1 + index] */
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data = bit | (bit << 8) | (bit << 16) | (bit << 24);
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iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
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}
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for (i = 0; i < VEC_COUNT / 4; i++) {
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/* Route to Node-0 Core-0 */
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if (index == 0)
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bit = BIT(cpu_logical_map(0));
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else
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bit = (eiointc_priv[index]->node << 4) | 1;
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data = bit | (bit << 8) | (bit << 16) | (bit << 24);
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iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
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}
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for (i = 0; i < VEC_COUNT / 32; i++) {
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data = 0xffffffff;
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iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
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iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
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}
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}
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return 0;
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}
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static void eiointc_irq_dispatch(struct irq_desc *desc)
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{
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int i;
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u64 pending;
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bool handled = false;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
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chained_irq_enter(chip, desc);
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for (i = 0; i < VEC_REG_COUNT; i++) {
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pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
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iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
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while (pending) {
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int bit = __ffs(pending);
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int irq = bit + VEC_COUNT_PER_REG * i;
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generic_handle_domain_irq(priv->eiointc_domain, irq);
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pending &= ~BIT(bit);
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handled = true;
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}
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}
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if (!handled)
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spurious_interrupt();
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chained_irq_exit(chip, desc);
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}
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static void eiointc_ack_irq(struct irq_data *d)
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{
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}
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static void eiointc_mask_irq(struct irq_data *d)
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{
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}
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static void eiointc_unmask_irq(struct irq_data *d)
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{
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}
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static struct irq_chip eiointc_irq_chip = {
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.name = "EIOINTC",
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.irq_ack = eiointc_ack_irq,
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.irq_mask = eiointc_mask_irq,
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.irq_unmask = eiointc_unmask_irq,
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.irq_set_affinity = eiointc_set_irq_affinity,
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};
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static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int ret;
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unsigned int i, type;
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unsigned long hwirq = 0;
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struct eiointc *priv = domain->host_data;
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ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; i++) {
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irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
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priv, handle_edge_irq, NULL, NULL);
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}
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return 0;
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}
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static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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int i;
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for (i = 0; i < nr_irqs; i++) {
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struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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irq_set_handler(virq + i, NULL);
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irq_domain_reset_irq_data(d);
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}
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}
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static const struct irq_domain_ops eiointc_domain_ops = {
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.translate = irq_domain_translate_onecell,
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.alloc = eiointc_domain_alloc,
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.free = eiointc_domain_free,
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};
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static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
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{
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int i;
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for (i = 0; i < MAX_IO_PICS; i++) {
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if (node == vec_group[i].node) {
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vec_group[i].parent = parent;
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return;
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}
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}
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}
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static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
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{
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int i;
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for (i = 0; i < MAX_IO_PICS; i++) {
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if (node == vec_group[i].node)
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return vec_group[i].parent;
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}
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return NULL;
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}
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static int __init pch_pic_parse_madt(union acpi_subtable_headers *header,
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const unsigned long end)
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{
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struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
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unsigned int node = (pchpic_entry->address >> 44) & 0xf;
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struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
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if (parent)
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return pch_pic_acpi_init(parent, pchpic_entry);
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return 0;
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}
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static int __init pch_msi_parse_madt(union acpi_subtable_headers *header,
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const unsigned long end)
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{
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struct irq_domain *parent;
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struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
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int node;
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if (cpu_has_flatmode)
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node = cpu_to_node(eiointc_priv[nr_pics - 1]->node * CORES_PER_EIO_NODE);
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else
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node = eiointc_priv[nr_pics - 1]->node;
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parent = acpi_get_vec_parent(node, msi_group);
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if (parent)
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return pch_msi_acpi_init(parent, pchmsi_entry);
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return 0;
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}
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static int __init acpi_cascade_irqdomain_init(void)
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{
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int r;
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r = acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC, pch_pic_parse_madt, 0);
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if (r < 0)
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return r;
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r = acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, pch_msi_parse_madt, 1);
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if (r < 0)
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return r;
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return 0;
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}
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int __init eiointc_acpi_init(struct irq_domain *parent,
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struct acpi_madt_eio_pic *acpi_eiointc)
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{
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int i, ret, parent_irq;
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unsigned long node_map;
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struct eiointc_priv *priv;
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int node;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->domain_handle = irq_domain_alloc_named_id_fwnode("EIOPIC",
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acpi_eiointc->node);
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if (!priv->domain_handle) {
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pr_err("Unable to allocate domain handle\n");
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goto out_free_priv;
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}
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priv->node = acpi_eiointc->node;
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node_map = acpi_eiointc->node_map ? : -1ULL;
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for_each_possible_cpu(i) {
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if (node_map & (1ULL << cpu_to_eio_node(i))) {
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node_set(cpu_to_eio_node(i), priv->node_map);
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cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
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}
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}
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/* Setup IRQ domain */
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priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
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&eiointc_domain_ops, priv);
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if (!priv->eiointc_domain) {
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pr_err("loongson-eiointc: cannot add IRQ domain\n");
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goto out_free_handle;
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}
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eiointc_priv[nr_pics++] = priv;
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eiointc_router_init(0);
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parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
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irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
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if (nr_pics == 1) {
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cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
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"irqchip/loongarch/intc:starting",
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eiointc_router_init, NULL);
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}
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if (cpu_has_flatmode)
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node = cpu_to_node(acpi_eiointc->node * CORES_PER_EIO_NODE);
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else
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node = acpi_eiointc->node;
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acpi_set_vec_parent(node, priv->eiointc_domain, pch_group);
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acpi_set_vec_parent(node, priv->eiointc_domain, msi_group);
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ret = acpi_cascade_irqdomain_init();
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return ret;
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out_free_handle:
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irq_domain_free_fwnode(priv->domain_handle);
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priv->domain_handle = NULL;
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out_free_priv:
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kfree(priv);
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return -ENOMEM;
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}
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