700 lines
16 KiB
Plaintext
700 lines
16 KiB
Plaintext
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# SPDX-License-Identifier: GPL-2.0-only
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menu "IRQ chip support"
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config IRQCHIP
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def_bool y
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depends on (OF_IRQ || ACPI_GENERIC_GSI)
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config ARM_GIC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config ARM_GIC_PM
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bool
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depends on PM
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select ARM_GIC
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config ARM_GIC_MAX_NR
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int
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depends on ARM_GIC
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default 2 if ARCH_REALVIEW
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default 1
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config ARM_GIC_V2M
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bool
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depends on PCI
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select ARM_GIC
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select PCI_MSI
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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select HAVE_ARM_SMCCC_DISCOVERY
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config ARM_GIC_V3_ITS
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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default ARM_GIC_V3
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config ARM_GIC_V3_ITS_PCI
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bool
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depends on ARM_GIC_V3_ITS
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depends on PCI
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depends on PCI_MSI
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default ARM_GIC_V3_ITS
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config ARM_GIC_V3_ITS_FSL_MC
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bool
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depends on ARM_GIC_V3_ITS
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depends on FSL_MC_BUS
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default ARM_GIC_V3_ITS
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config ARM_NVIC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ARMADA_370_XP_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select PCI_MSI if PCI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config ALPINE_MSI
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bool
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depends on PCI
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select PCI_MSI
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select GENERIC_IRQ_CHIP
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config AL_FIC
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bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
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depends on OF || COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
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Support Amazon's Annapurna Labs Fabric Interrupt Controller.
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select SPARSE_IRQ
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config I8259
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bool
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select IRQ_DOMAIN
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config BCM6345_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config BCM7038_L1_IRQ
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tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
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depends on ARCH_BRCMSTB || BMIPS_GENERIC
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default ARCH_BRCMSTB || BMIPS_GENERIC
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config BCM7120_L2_IRQ
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tristate "Broadcom STB 7120-style L2 interrupt controller driver"
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depends on ARCH_BRCMSTB || BMIPS_GENERIC
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default ARCH_BRCMSTB || BMIPS_GENERIC
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
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tristate "Broadcom STB generic L2 interrupt controller driver"
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depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
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default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_AINTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_CP_INTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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config FARADAY_FTINTC010
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bool
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select IRQ_DOMAIN
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select SPARSE_IRQ
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config IXP4XX_IRQ
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bool
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select IRQ_DOMAIN
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select SPARSE_IRQ
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config MADERA_IRQ
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tristate
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config IRQ_MIPS_CPU
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bool
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select SPARSE_IRQ
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default y
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config OMPIC
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bool
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC" if COMPILE_TEST
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depends on OF
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select IRQ_DOMAIN
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help
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Support for the J-Core integrated AIC.
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config RDA_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_INTC_IRQPIN
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bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
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select IRQ_DOMAIN
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help
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Enable support for the Renesas Interrupt Controller for external
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interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
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config RENESAS_IRQC
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bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
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Enable support for the Renesas Interrupt Controller for external
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devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
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config RENESAS_RZA1_IRQC
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bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
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select IRQ_DOMAIN_HIERARCHY
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help
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Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
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to 8 external interrupts with configurable sense select.
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config RENESAS_RZG2L_IRQC
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bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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help
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Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
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for external devices.
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config SL28CPLD_INTC
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bool "Kontron sl28cpld IRQ controller"
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depends on MFD_SL28CPLD=y || COMPILE_TEST
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select REGMAP_IRQ
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help
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Interrupt controller driver for the board management controller
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found on the Kontron sl28 CPLD.
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config ST_IRQCHIP
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bool
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select REGMAP
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select MFD_SYSCON
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help
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Enables SysCfg Controlled IRQs on STi based platforms.
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config SUN4I_INTC
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bool
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config SUN6I_R_INTC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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config SUNXI_NMI_INTC
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bool
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select GENERIC_IRQ_CHIP
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TS4800_IRQ
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tristate "TS-4800 IRQ controller"
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select IRQ_DOMAIN
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depends on HAS_IOMEM
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depends on SOC_IMX51 || COMPILE_TEST
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help
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Support for the TS-4800 FPGA IRQ controller
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config XILINX_INTC
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bool "Xilinx Interrupt Controller IP"
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depends on OF_ADDRESS
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select IRQ_DOMAIN
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help
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Support for the Xilinx Interrupt Controller IP core.
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This is used as a primary controller with MicroBlaze and can also
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be used as a secondary chained controller on other platforms.
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MIPS_GIC
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bool
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select GENERIC_IRQ_IPI if SMP
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select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
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config INGENIC_IRQ
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bool
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depends on MACH_INGENIC
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default y
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config INGENIC_TCU_IRQ
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bool "Ingenic JZ47xx TCU interrupt controller"
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default MACH_INGENIC
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depends on MIPS || COMPILE_TEST
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select MFD_SYSCON
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select GENERIC_IRQ_CHIP
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help
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Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
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JZ47xx SoCs.
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If unsure, say N.
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config IMX_GPCV2
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bool
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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config MSCC_OCELOT_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config MVEBU_GICP
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bool
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config MVEBU_ICU
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bool
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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config MVEBU_PIC
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bool
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config MVEBU_SEI
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bool
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config LS_EXTIRQ
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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select MFD_SYSCON
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI
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config PARTITION_PERCPU
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bool
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config QCOM_IRQ_COMBINER
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bool "QCOM IRQ combiner support"
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depends on ARCH_QCOM && ACPI
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select IRQ_DOMAIN_HIERARCHY
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help
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Say yes here to add support for the IRQ combiner devices embedded
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in Qualcomm Technologies chips.
|
||
|
|
|
||
|
|
config IRQ_UNIPHIER_AIDET
|
||
|
|
bool "UniPhier AIDET support" if COMPILE_TEST
|
||
|
|
depends on ARCH_UNIPHIER || COMPILE_TEST
|
||
|
|
default ARCH_UNIPHIER
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Support for the UniPhier AIDET (ARM Interrupt Detector).
|
||
|
|
|
||
|
|
config MESON_IRQ_GPIO
|
||
|
|
tristate "Meson GPIO Interrupt Multiplexer"
|
||
|
|
depends on ARCH_MESON || COMPILE_TEST
|
||
|
|
default ARCH_MESON
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Support Meson SoC Family GPIO Interrupt Multiplexer
|
||
|
|
|
||
|
|
config GOLDFISH_PIC
|
||
|
|
bool "Goldfish programmable interrupt controller"
|
||
|
|
depends on MIPS && (GOLDFISH || COMPILE_TEST)
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
help
|
||
|
|
Say yes here to enable Goldfish interrupt controller driver used
|
||
|
|
for Goldfish based virtual platforms.
|
||
|
|
|
||
|
|
config QCOM_PDC
|
||
|
|
tristate "QCOM PDC"
|
||
|
|
depends on ARCH_QCOM
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Power Domain Controller driver to manage and configure wakeup
|
||
|
|
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
|
||
|
|
|
||
|
|
config QCOM_MPM
|
||
|
|
tristate "QCOM MPM"
|
||
|
|
depends on ARCH_QCOM
|
||
|
|
depends on MAILBOX
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
MSM Power Manager driver to manage and configure wakeup
|
||
|
|
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
|
||
|
|
|
||
|
|
config CSKY_MPINTC
|
||
|
|
bool
|
||
|
|
depends on CSKY
|
||
|
|
help
|
||
|
|
Say yes here to enable C-SKY SMP interrupt controller driver used
|
||
|
|
for C-SKY SMP system.
|
||
|
|
In fact it's not mmio map in hardware and it uses ld/st to visit the
|
||
|
|
controller's register inside CPU.
|
||
|
|
|
||
|
|
config CSKY_APB_INTC
|
||
|
|
bool "C-SKY APB Interrupt Controller"
|
||
|
|
depends on CSKY
|
||
|
|
help
|
||
|
|
Say yes here to enable C-SKY APB interrupt controller driver used
|
||
|
|
by C-SKY single core SOC system. It uses mmio map apb-bus to visit
|
||
|
|
the controller's register.
|
||
|
|
|
||
|
|
config IMX_IRQSTEER
|
||
|
|
bool "i.MX IRQSTEER support"
|
||
|
|
depends on ARCH_MXC || COMPILE_TEST
|
||
|
|
default ARCH_MXC
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
help
|
||
|
|
Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
|
||
|
|
|
||
|
|
config IMX_INTMUX
|
||
|
|
bool "i.MX INTMUX support" if COMPILE_TEST
|
||
|
|
default y if ARCH_MXC
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
help
|
||
|
|
Support for the i.MX INTMUX interrupt multiplexer.
|
||
|
|
|
||
|
|
config IMX_MU_MSI
|
||
|
|
tristate "i.MX MU used as MSI controller"
|
||
|
|
depends on OF && HAS_IOMEM
|
||
|
|
depends on ARCH_MXC || COMPILE_TEST
|
||
|
|
default m if ARCH_MXC
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
select GENERIC_MSI_IRQ_DOMAIN
|
||
|
|
help
|
||
|
|
Provide a driver for the i.MX Messaging Unit block used as a
|
||
|
|
CPU-to-CPU MSI controller. This requires a specially crafted DT
|
||
|
|
to make use of this driver.
|
||
|
|
|
||
|
|
If unsure, say N
|
||
|
|
|
||
|
|
config LS1X_IRQ
|
||
|
|
bool "Loongson-1 Interrupt Controller"
|
||
|
|
depends on MACH_LOONGSON32
|
||
|
|
default y
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
help
|
||
|
|
Support for the Loongson-1 platform Interrupt Controller.
|
||
|
|
|
||
|
|
config TI_SCI_INTR_IRQCHIP
|
||
|
|
bool
|
||
|
|
depends on TI_SCI_PROTOCOL
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
This enables the irqchip driver support for K3 Interrupt router
|
||
|
|
over TI System Control Interface available on some new TI's SoCs.
|
||
|
|
If you wish to use interrupt router irq resources managed by the
|
||
|
|
TI System Controller, say Y here. Otherwise, say N.
|
||
|
|
|
||
|
|
config TI_SCI_INTA_IRQCHIP
|
||
|
|
bool
|
||
|
|
depends on TI_SCI_PROTOCOL
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
select TI_SCI_INTA_MSI_DOMAIN
|
||
|
|
help
|
||
|
|
This enables the irqchip driver support for K3 Interrupt aggregator
|
||
|
|
over TI System Control Interface available on some new TI's SoCs.
|
||
|
|
If you wish to use interrupt aggregator irq resources managed by the
|
||
|
|
TI System Controller, say Y here. Otherwise, say N.
|
||
|
|
|
||
|
|
config TI_PRUSS_INTC
|
||
|
|
tristate
|
||
|
|
depends on TI_PRUSS
|
||
|
|
default TI_PRUSS
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
help
|
||
|
|
This enables support for the PRU-ICSS Local Interrupt Controller
|
||
|
|
present within a PRU-ICSS subsystem present on various TI SoCs.
|
||
|
|
The PRUSS INTC enables various interrupts to be routed to multiple
|
||
|
|
different processors within the SoC.
|
||
|
|
|
||
|
|
config RISCV_INTC
|
||
|
|
bool "RISC-V Local Interrupt Controller"
|
||
|
|
depends on RISCV
|
||
|
|
default y
|
||
|
|
help
|
||
|
|
This enables support for the per-HART local interrupt controller
|
||
|
|
found in standard RISC-V systems. The per-HART local interrupt
|
||
|
|
controller handles timer interrupts, software interrupts, and
|
||
|
|
hardware interrupts. Without a per-HART local interrupt controller,
|
||
|
|
a RISC-V system will be unable to handle any interrupts.
|
||
|
|
|
||
|
|
If you don't know what to do here, say Y.
|
||
|
|
|
||
|
|
config SIFIVE_PLIC
|
||
|
|
bool "SiFive Platform-Level Interrupt Controller"
|
||
|
|
depends on RISCV
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
|
||
|
|
help
|
||
|
|
This enables support for the PLIC chip found in SiFive (and
|
||
|
|
potentially other) RISC-V systems. The PLIC controls devices
|
||
|
|
interrupts and connects them to each core's local interrupt
|
||
|
|
controller. Aside from timer and software interrupts, all other
|
||
|
|
interrupt sources are subordinate to the PLIC.
|
||
|
|
|
||
|
|
If you don't know what to do here, say Y.
|
||
|
|
|
||
|
|
config EXYNOS_IRQ_COMBINER
|
||
|
|
bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
|
||
|
|
depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
|
||
|
|
help
|
||
|
|
Say yes here to add support for the IRQ combiner devices embedded
|
||
|
|
in Samsung Exynos chips.
|
||
|
|
|
||
|
|
config IRQ_LOONGARCH_CPU
|
||
|
|
bool
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
||
|
|
select LOONGSON_LIOINTC
|
||
|
|
select LOONGSON_EIOINTC
|
||
|
|
select LOONGSON_PCH_PIC
|
||
|
|
select LOONGSON_PCH_MSI
|
||
|
|
select LOONGSON_PCH_LPC
|
||
|
|
help
|
||
|
|
Support for the LoongArch CPU Interrupt Controller. For details of
|
||
|
|
irq chip hierarchy on LoongArch platforms please read the document
|
||
|
|
Documentation/loongarch/irq-chip-model.rst.
|
||
|
|
|
||
|
|
config LOONGSON_LIOINTC
|
||
|
|
bool "Loongson Local I/O Interrupt Controller"
|
||
|
|
depends on MACH_LOONGSON64
|
||
|
|
default y
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
help
|
||
|
|
Support for the Loongson Local I/O Interrupt Controller.
|
||
|
|
|
||
|
|
config LOONGSON_EIOINTC
|
||
|
|
bool "Loongson Extend I/O Interrupt Controller"
|
||
|
|
depends on LOONGARCH
|
||
|
|
depends on MACH_LOONGSON64
|
||
|
|
default MACH_LOONGSON64
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
help
|
||
|
|
Support for the Loongson3 Extend I/O Interrupt Vector Controller.
|
||
|
|
|
||
|
|
config LOONGSON_HTPIC
|
||
|
|
bool "Loongson3 HyperTransport PIC Controller"
|
||
|
|
depends on MACH_LOONGSON64 && MIPS
|
||
|
|
default y
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
help
|
||
|
|
Support for the Loongson-3 HyperTransport PIC Controller.
|
||
|
|
|
||
|
|
config LOONGSON_HTVEC
|
||
|
|
bool "Loongson HyperTransport Interrupt Vector Controller"
|
||
|
|
depends on MACH_LOONGSON64
|
||
|
|
default MACH_LOONGSON64
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Support for the Loongson HyperTransport Interrupt Vector Controller.
|
||
|
|
|
||
|
|
config LOONGSON_PCH_PIC
|
||
|
|
bool "Loongson PCH PIC Controller"
|
||
|
|
depends on MACH_LOONGSON64
|
||
|
|
default MACH_LOONGSON64
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
select IRQ_FASTEOI_HIERARCHY_HANDLERS
|
||
|
|
help
|
||
|
|
Support for the Loongson PCH PIC Controller.
|
||
|
|
|
||
|
|
config LOONGSON_PCH_MSI
|
||
|
|
bool "Loongson PCH MSI Controller"
|
||
|
|
depends on MACH_LOONGSON64
|
||
|
|
depends on PCI
|
||
|
|
default MACH_LOONGSON64
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
select PCI_MSI
|
||
|
|
help
|
||
|
|
Support for the Loongson PCH MSI Controller.
|
||
|
|
|
||
|
|
config LOONGSON_PCH_LPC
|
||
|
|
bool "Loongson PCH LPC Controller"
|
||
|
|
depends on LOONGARCH
|
||
|
|
depends on MACH_LOONGSON64
|
||
|
|
default MACH_LOONGSON64
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Support for the Loongson PCH LPC Controller.
|
||
|
|
|
||
|
|
config MST_IRQ
|
||
|
|
bool "MStar Interrupt Controller"
|
||
|
|
depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
|
||
|
|
default ARCH_MEDIATEK
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Support MStar Interrupt Controller.
|
||
|
|
|
||
|
|
config WPCM450_AIC
|
||
|
|
bool "Nuvoton WPCM450 Advanced Interrupt Controller"
|
||
|
|
depends on ARCH_WPCM450
|
||
|
|
help
|
||
|
|
Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
|
||
|
|
|
||
|
|
config IRQ_IDT3243X
|
||
|
|
bool
|
||
|
|
select GENERIC_IRQ_CHIP
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
|
||
|
|
config APPLE_AIC
|
||
|
|
bool "Apple Interrupt Controller (AIC)"
|
||
|
|
depends on ARM64
|
||
|
|
depends on ARCH_APPLE || COMPILE_TEST
|
||
|
|
help
|
||
|
|
Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
|
||
|
|
such as the M1.
|
||
|
|
|
||
|
|
config MCHP_EIC
|
||
|
|
bool "Microchip External Interrupt Controller"
|
||
|
|
depends on ARCH_AT91 || COMPILE_TEST
|
||
|
|
select IRQ_DOMAIN
|
||
|
|
select IRQ_DOMAIN_HIERARCHY
|
||
|
|
help
|
||
|
|
Support for Microchip External Interrupt Controller.
|
||
|
|
|
||
|
|
config SUNPLUS_SP7021_INTC
|
||
|
|
bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
|
||
|
|
default SOC_SP7021
|
||
|
|
help
|
||
|
|
Support for the Sunplus SP7021 Interrupt Controller IP core.
|
||
|
|
SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
|
||
|
|
chained controller, routing all interrupt source in P-Chip to
|
||
|
|
the primary controller on C-Chip.
|
||
|
|
|
||
|
|
endmenu
|