434 lines
9.0 KiB
ArmAsm
434 lines
9.0 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains sleep low-level functions for PowerBook G3.
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* Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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* and Paul Mackerras (paulus@samba.org).
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/mmu.h>
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#include <asm/feature-fixups.h>
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#define MAGIC 0x4c617273 /* 'Lars' */
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/*
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* Structure for storing CPU registers on the stack.
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*/
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#define SL_SP 0
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#define SL_PC 4
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#define SL_MSR 8
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#define SL_SDR1 0xc
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#define SL_SPRG0 0x10 /* 4 sprg's */
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#define SL_DBAT0 0x20
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#define SL_IBAT0 0x28
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#define SL_DBAT1 0x30
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#define SL_IBAT1 0x38
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#define SL_DBAT2 0x40
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#define SL_IBAT2 0x48
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#define SL_DBAT3 0x50
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#define SL_IBAT3 0x58
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#define SL_DBAT4 0x60
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#define SL_IBAT4 0x68
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#define SL_DBAT5 0x70
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#define SL_IBAT5 0x78
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#define SL_DBAT6 0x80
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#define SL_IBAT6 0x88
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#define SL_DBAT7 0x90
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#define SL_IBAT7 0x98
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#define SL_TB 0xa0
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#define SL_R2 0xa8
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#define SL_CR 0xac
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#define SL_LR 0xb0
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#define SL_R12 0xb4 /* r12 to r31 */
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#define SL_SIZE (SL_R12 + 80)
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.section .text
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.align 5
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#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
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(defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
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/* This gets called by via-pmu.c late during the sleep process.
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* The PMU was already send the sleep command and will shut us down
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* soon. We need to save all that is needed and setup the wakeup
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* vector that will be called by the ROM on wakeup
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*/
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_GLOBAL(low_sleep_handler)
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#ifndef CONFIG_PPC_BOOK3S_32
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blr
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#else
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mflr r0
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lis r11,sleep_storage@ha
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addi r11,r11,sleep_storage@l
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stw r0,SL_LR(r11)
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mfcr r0
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stw r0,SL_CR(r11)
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stw r1,SL_SP(r11)
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stw r2,SL_R2(r11)
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stmw r12,SL_R12(r11)
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/* Save MSR & SDR1 */
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mfmsr r4
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stw r4,SL_MSR(r11)
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mfsdr1 r4
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stw r4,SL_SDR1(r11)
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/* Get a stable timebase and save it */
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1: mftbu r4
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stw r4,SL_TB(r11)
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mftb r5
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stw r5,SL_TB+4(r11)
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mftbu r3
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cmpw r3,r4
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bne 1b
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/* Save SPRGs */
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mfsprg r4,0
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stw r4,SL_SPRG0(r11)
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mfsprg r4,1
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stw r4,SL_SPRG0+4(r11)
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mfsprg r4,2
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stw r4,SL_SPRG0+8(r11)
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mfsprg r4,3
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stw r4,SL_SPRG0+12(r11)
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/* Save BATs */
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mfdbatu r4,0
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stw r4,SL_DBAT0(r11)
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mfdbatl r4,0
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stw r4,SL_DBAT0+4(r11)
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mfdbatu r4,1
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stw r4,SL_DBAT1(r11)
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mfdbatl r4,1
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stw r4,SL_DBAT1+4(r11)
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mfdbatu r4,2
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stw r4,SL_DBAT2(r11)
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mfdbatl r4,2
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stw r4,SL_DBAT2+4(r11)
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mfdbatu r4,3
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stw r4,SL_DBAT3(r11)
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mfdbatl r4,3
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stw r4,SL_DBAT3+4(r11)
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mfibatu r4,0
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stw r4,SL_IBAT0(r11)
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mfibatl r4,0
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stw r4,SL_IBAT0+4(r11)
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mfibatu r4,1
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stw r4,SL_IBAT1(r11)
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mfibatl r4,1
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stw r4,SL_IBAT1+4(r11)
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mfibatu r4,2
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stw r4,SL_IBAT2(r11)
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mfibatl r4,2
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stw r4,SL_IBAT2+4(r11)
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mfibatu r4,3
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stw r4,SL_IBAT3(r11)
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mfibatl r4,3
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stw r4,SL_IBAT3+4(r11)
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BEGIN_MMU_FTR_SECTION
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mfspr r4,SPRN_DBAT4U
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stw r4,SL_DBAT4(r11)
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mfspr r4,SPRN_DBAT4L
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stw r4,SL_DBAT4+4(r11)
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mfspr r4,SPRN_DBAT5U
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stw r4,SL_DBAT5(r11)
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mfspr r4,SPRN_DBAT5L
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stw r4,SL_DBAT5+4(r11)
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mfspr r4,SPRN_DBAT6U
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stw r4,SL_DBAT6(r11)
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mfspr r4,SPRN_DBAT6L
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stw r4,SL_DBAT6+4(r11)
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mfspr r4,SPRN_DBAT7U
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stw r4,SL_DBAT7(r11)
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mfspr r4,SPRN_DBAT7L
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stw r4,SL_DBAT7+4(r11)
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mfspr r4,SPRN_IBAT4U
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stw r4,SL_IBAT4(r11)
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mfspr r4,SPRN_IBAT4L
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stw r4,SL_IBAT4+4(r11)
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mfspr r4,SPRN_IBAT5U
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stw r4,SL_IBAT5(r11)
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mfspr r4,SPRN_IBAT5L
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stw r4,SL_IBAT5+4(r11)
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mfspr r4,SPRN_IBAT6U
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stw r4,SL_IBAT6(r11)
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mfspr r4,SPRN_IBAT6L
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stw r4,SL_IBAT6+4(r11)
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mfspr r4,SPRN_IBAT7U
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stw r4,SL_IBAT7(r11)
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mfspr r4,SPRN_IBAT7L
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stw r4,SL_IBAT7+4(r11)
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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/* Backup various CPU config stuffs */
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bl __save_cpu_setup
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/* The ROM can wake us up via 2 different vectors:
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* - On wallstreet & lombard, we must write a magic
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* value 'Lars' at address 4 and a pointer to a
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* memory location containing the PC to resume from
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* at address 0.
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* - On Core99, we must store the wakeup vector at
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* address 0x80 and eventually it's parameters
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* at address 0x84. I've have some trouble with those
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* parameters however and I no longer use them.
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*/
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lis r5,grackle_wake_up@ha
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addi r5,r5,grackle_wake_up@l
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tophys(r5,r5)
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stw r5,SL_PC(r11)
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lis r4,KERNELBASE@h
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tophys(r5,r11)
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addi r5,r5,SL_PC
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lis r6,MAGIC@ha
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addi r6,r6,MAGIC@l
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stw r5,0(r4)
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stw r6,4(r4)
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/* Setup stuffs at 0x80-0x84 for Core99 */
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lis r3,core99_wake_up@ha
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addi r3,r3,core99_wake_up@l
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tophys(r3,r3)
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stw r3,0x80(r4)
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stw r5,0x84(r4)
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.globl low_cpu_offline_self
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low_cpu_offline_self:
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/* Flush & disable all caches */
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bl flush_disable_caches
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/* Turn off data relocation. */
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mfmsr r3 /* Save MSR in r7 */
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rlwinm r3,r3,0,28,26 /* Turn off DR bit */
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sync
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mtmsr r3
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isync
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BEGIN_FTR_SECTION
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/* Flush any pending L2 data prefetches to work around HW bug */
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sync
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lis r3,0xfff0
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lwz r0,0(r3) /* perform cache-inhibited load to ROM */
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sync /* (caches are disabled at this point) */
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END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
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/*
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* Set the HID0 and MSR for sleep.
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*/
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mfspr r2,SPRN_HID0
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rlwinm r2,r2,0,10,7 /* clear doze, nap */
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oris r2,r2,HID0_SLEEP@h
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sync
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isync
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mtspr SPRN_HID0,r2
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sync
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/* This loop puts us back to sleep in case we have a spurrious
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* wakeup so that the host bridge properly stays asleep. The
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* CPU will be turned off, either after a known time (about 1
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* second) on wallstreet & lombard, or as soon as the CPU enters
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* SLEEP mode on core99
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*/
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mfmsr r2
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oris r2,r2,MSR_POW@h
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1: sync
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mtmsr r2
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isync
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b 1b
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_ASM_NOKPROBE_SYMBOL(low_cpu_offline_self)
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/*
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* Here is the resume code.
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*/
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/*
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* Core99 machines resume here
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* r4 has the physical address of SL_PC(sp) (unused)
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*/
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_GLOBAL(core99_wake_up)
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/* Make sure HID0 no longer contains any sleep bit and that data cache
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* is disabled
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*/
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mfspr r3,SPRN_HID0
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rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
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rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
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mtspr SPRN_HID0,r3
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sync
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isync
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/* sanitize MSR */
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mfmsr r3
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ori r3,r3,MSR_EE|MSR_IP
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xori r3,r3,MSR_EE|MSR_IP
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sync
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isync
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mtmsr r3
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sync
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isync
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/* Recover sleep storage */
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lis r3,sleep_storage@ha
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addi r3,r3,sleep_storage@l
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tophys(r3,r3)
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addi r1,r3,SL_PC
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/* Pass thru to older resume code ... */
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_ASM_NOKPROBE_SYMBOL(core99_wake_up)
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/*
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* Here is the resume code for older machines.
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* r1 has the physical address of SL_PC(sp).
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*/
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grackle_wake_up:
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/* Restore the kernel's segment registers before
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* we do any r1 memory access as we are not sure they
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* are in a sane state above the first 256Mb region
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*/
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bl load_segment_registers
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sync
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isync
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subi r1,r1,SL_PC
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/* Restore various CPU config stuffs */
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bl __restore_cpu_setup
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/* Make sure all FPRs have been initialized */
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bl reloc_offset
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bl __init_fpu_registers
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/* Invalidate & enable L1 cache, we don't care about
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* whatever the ROM may have tried to write to memory
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*/
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bl __inval_enable_L1
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/* Restore the BATs, and SDR1. Then we can turn on the MMU. */
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lwz r4,SL_SDR1(r1)
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mtsdr1 r4
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lwz r4,SL_SPRG0(r1)
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mtsprg 0,r4
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lwz r4,SL_SPRG0+4(r1)
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mtsprg 1,r4
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lwz r4,SL_SPRG0+8(r1)
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mtsprg 2,r4
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lwz r4,SL_SPRG0+12(r1)
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mtsprg 3,r4
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lwz r4,SL_DBAT0(r1)
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mtdbatu 0,r4
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lwz r4,SL_DBAT0+4(r1)
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mtdbatl 0,r4
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lwz r4,SL_DBAT1(r1)
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mtdbatu 1,r4
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lwz r4,SL_DBAT1+4(r1)
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mtdbatl 1,r4
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lwz r4,SL_DBAT2(r1)
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mtdbatu 2,r4
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lwz r4,SL_DBAT2+4(r1)
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mtdbatl 2,r4
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lwz r4,SL_DBAT3(r1)
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mtdbatu 3,r4
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lwz r4,SL_DBAT3+4(r1)
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mtdbatl 3,r4
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lwz r4,SL_IBAT0(r1)
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mtibatu 0,r4
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lwz r4,SL_IBAT0+4(r1)
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mtibatl 0,r4
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lwz r4,SL_IBAT1(r1)
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mtibatu 1,r4
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lwz r4,SL_IBAT1+4(r1)
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mtibatl 1,r4
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lwz r4,SL_IBAT2(r1)
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mtibatu 2,r4
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lwz r4,SL_IBAT2+4(r1)
|
||
|
|
mtibatl 2,r4
|
||
|
|
lwz r4,SL_IBAT3(r1)
|
||
|
|
mtibatu 3,r4
|
||
|
|
lwz r4,SL_IBAT3+4(r1)
|
||
|
|
mtibatl 3,r4
|
||
|
|
|
||
|
|
BEGIN_MMU_FTR_SECTION
|
||
|
|
lwz r4,SL_DBAT4(r1)
|
||
|
|
mtspr SPRN_DBAT4U,r4
|
||
|
|
lwz r4,SL_DBAT4+4(r1)
|
||
|
|
mtspr SPRN_DBAT4L,r4
|
||
|
|
lwz r4,SL_DBAT5(r1)
|
||
|
|
mtspr SPRN_DBAT5U,r4
|
||
|
|
lwz r4,SL_DBAT5+4(r1)
|
||
|
|
mtspr SPRN_DBAT5L,r4
|
||
|
|
lwz r4,SL_DBAT6(r1)
|
||
|
|
mtspr SPRN_DBAT6U,r4
|
||
|
|
lwz r4,SL_DBAT6+4(r1)
|
||
|
|
mtspr SPRN_DBAT6L,r4
|
||
|
|
lwz r4,SL_DBAT7(r1)
|
||
|
|
mtspr SPRN_DBAT7U,r4
|
||
|
|
lwz r4,SL_DBAT7+4(r1)
|
||
|
|
mtspr SPRN_DBAT7L,r4
|
||
|
|
lwz r4,SL_IBAT4(r1)
|
||
|
|
mtspr SPRN_IBAT4U,r4
|
||
|
|
lwz r4,SL_IBAT4+4(r1)
|
||
|
|
mtspr SPRN_IBAT4L,r4
|
||
|
|
lwz r4,SL_IBAT5(r1)
|
||
|
|
mtspr SPRN_IBAT5U,r4
|
||
|
|
lwz r4,SL_IBAT5+4(r1)
|
||
|
|
mtspr SPRN_IBAT5L,r4
|
||
|
|
lwz r4,SL_IBAT6(r1)
|
||
|
|
mtspr SPRN_IBAT6U,r4
|
||
|
|
lwz r4,SL_IBAT6+4(r1)
|
||
|
|
mtspr SPRN_IBAT6L,r4
|
||
|
|
lwz r4,SL_IBAT7(r1)
|
||
|
|
mtspr SPRN_IBAT7U,r4
|
||
|
|
lwz r4,SL_IBAT7+4(r1)
|
||
|
|
mtspr SPRN_IBAT7L,r4
|
||
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
|
||
|
|
|
||
|
|
/* Flush all TLBs */
|
||
|
|
lis r4,0x1000
|
||
|
|
1: addic. r4,r4,-0x1000
|
||
|
|
tlbie r4
|
||
|
|
blt 1b
|
||
|
|
sync
|
||
|
|
|
||
|
|
/* Restore TB */
|
||
|
|
li r3,0
|
||
|
|
mttbl r3
|
||
|
|
lwz r3,SL_TB(r1)
|
||
|
|
lwz r4,SL_TB+4(r1)
|
||
|
|
mttbu r3
|
||
|
|
mttbl r4
|
||
|
|
|
||
|
|
/* Restore the callee-saved registers and return */
|
||
|
|
lwz r0,SL_CR(r1)
|
||
|
|
mtcr r0
|
||
|
|
lwz r2,SL_R2(r1)
|
||
|
|
lmw r12,SL_R12(r1)
|
||
|
|
|
||
|
|
/* restore the MSR and SP and turn on the MMU and return */
|
||
|
|
lwz r3,SL_MSR(r1)
|
||
|
|
lwz r4,SL_LR(r1)
|
||
|
|
lwz r1,SL_SP(r1)
|
||
|
|
mtsrr0 r4
|
||
|
|
mtsrr1 r3
|
||
|
|
sync
|
||
|
|
isync
|
||
|
|
rfi
|
||
|
|
_ASM_NOKPROBE_SYMBOL(grackle_wake_up)
|
||
|
|
|
||
|
|
#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
|
||
|
|
|
||
|
|
.section .bss
|
||
|
|
.balign L1_CACHE_BYTES
|
||
|
|
sleep_storage:
|
||
|
|
.space SL_SIZE
|
||
|
|
.balign L1_CACHE_BYTES, 0
|
||
|
|
|
||
|
|
#endif /* CONFIG_PPC_BOOK3S_32 */
|
||
|
|
.section .text
|