94 lines
3.2 KiB
C
94 lines
3.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Performance counter support for POWER8 processors.
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*
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* Copyright 2014 Sukadev Bhattiprolu, IBM Corporation.
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*/
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/*
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* Power8 event codes.
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*/
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EVENT(PM_CYC, 0x0001e)
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EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
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EVENT(PM_CMPLU_STALL, 0x4000a)
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EVENT(PM_INST_CMPL, 0x00002)
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EVENT(PM_BRU_FIN, 0x10068)
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EVENT(PM_BR_MPRED_CMPL, 0x400f6)
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/* All L1 D cache load references counted at finish, gated by reject */
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EVENT(PM_LD_REF_L1, 0x100ee)
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/* Load Missed L1 */
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EVENT(PM_LD_MISS_L1, 0x3e054)
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/* Store Missed L1 */
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EVENT(PM_ST_MISS_L1, 0x300f0)
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/* L1 cache data prefetches */
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EVENT(PM_L1_PREF, 0x0d8b8)
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/* Instruction fetches from L1 */
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EVENT(PM_INST_FROM_L1, 0x04080)
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/* Demand iCache Miss */
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EVENT(PM_L1_ICACHE_MISS, 0x200fd)
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/* Instruction Demand sectors wriittent into IL1 */
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EVENT(PM_L1_DEMAND_WRITE, 0x0408c)
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/* Instruction prefetch written into IL1 */
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EVENT(PM_IC_PREF_WRITE, 0x0408e)
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/* The data cache was reloaded from local core's L3 due to a demand load */
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EVENT(PM_DATA_FROM_L3, 0x4c042)
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe)
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/* All successful D-side store dispatches for this thread */
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EVENT(PM_L2_ST, 0x17080)
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/* All successful D-side store dispatches for this thread that were L2 Miss */
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EVENT(PM_L2_ST_MISS, 0x17082)
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/* Total HW L3 prefetches(Load+store) */
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EVENT(PM_L3_PREF_ALL, 0x4e052)
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/* Data PTEG reload */
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EVENT(PM_DTLB_MISS, 0x300fc)
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/* ITLB Reloaded */
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EVENT(PM_ITLB_MISS, 0x400fc)
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/* Run_Instructions */
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EVENT(PM_RUN_INST_CMPL, 0x500fa)
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/* Alternate event code for PM_RUN_INST_CMPL */
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EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa)
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/* Run_cycles */
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EVENT(PM_RUN_CYC, 0x600f4)
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/* Alternate event code for Run_cycles */
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EVENT(PM_RUN_CYC_ALT, 0x200f4)
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/* Marked store completed */
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EVENT(PM_MRK_ST_CMPL, 0x10134)
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/* Alternate event code for Marked store completed */
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EVENT(PM_MRK_ST_CMPL_ALT, 0x301e2)
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/* Marked two path branch */
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EVENT(PM_BR_MRK_2PATH, 0x10138)
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/* Alternate event code for PM_BR_MRK_2PATH */
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EVENT(PM_BR_MRK_2PATH_ALT, 0x40138)
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/* L3 castouts in Mepf state */
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EVENT(PM_L3_CO_MEPF, 0x18082)
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/* Alternate event code for PM_L3_CO_MEPF */
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EVENT(PM_L3_CO_MEPF_ALT, 0x3e05e)
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/* Data cache was reloaded from a location other than L2 due to a marked load */
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EVENT(PM_MRK_DATA_FROM_L2MISS, 0x1d14e)
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/* Alternate event code for PM_MRK_DATA_FROM_L2MISS */
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EVENT(PM_MRK_DATA_FROM_L2MISS_ALT, 0x401e8)
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/* Alternate event code for PM_CMPLU_STALL */
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EVENT(PM_CMPLU_STALL_ALT, 0x1e054)
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/* Two path branch */
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EVENT(PM_BR_2PATH, 0x20036)
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/* Alternate event code for PM_BR_2PATH */
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EVENT(PM_BR_2PATH_ALT, 0x40036)
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/* # PPC Dispatched */
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EVENT(PM_INST_DISP, 0x200f2)
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/* Alternate event code for PM_INST_DISP */
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EVENT(PM_INST_DISP_ALT, 0x300f2)
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/* Marked filter Match */
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EVENT(PM_MRK_FILT_MATCH, 0x2013c)
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/* Alternate event code for PM_MRK_FILT_MATCH */
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EVENT(PM_MRK_FILT_MATCH_ALT, 0x3012e)
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/* Alternate event code for PM_LD_MISS_L1 */
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EVENT(PM_LD_MISS_L1_ALT, 0x400f0)
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/*
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* Memory Access Event -- mem_access
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* Primary PMU event used here is PM_MRK_INST_CMPL, along with
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* Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]).
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*/
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EVENT(MEM_ACCESS, 0x10401e0)
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