30 lines
1012 B
C
30 lines
1012 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _PARISC_DMA_MAPPING_H
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#define _PARISC_DMA_MAPPING_H
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/*
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** We need to support 4 different coherent dma models with one binary:
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**
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** I/O MMU consistent method dma_sync behavior
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** ============= ====================== =======================
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** a) PA-7x00LC uncachable host memory flush/purge
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** b) U2/Uturn cachable host memory NOP
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** c) Ike/Astro cachable host memory NOP
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** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel
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**
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** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
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**
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** Systems (eg PCX-T workstations) that don't fall into the above
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** categories will need to modify the needed drivers to perform
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** flush/purge and allocate "regular" cacheable pages for everything.
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*/
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extern const struct dma_map_ops *hppa_dma_ops;
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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{
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return hppa_dma_ops;
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}
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#endif
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