311 lines
8.0 KiB
C
311 lines
8.0 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
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*/
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#ifndef __ASM_JAZZ_H
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#define __ASM_JAZZ_H
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/*
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* The addresses below are virtual address. The mappings are
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* created on startup via wired entries in the tlb. The Mips
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* Magnum R3000 and R4000 machines are similar in many aspects,
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* but many hardware register are accessible at 0xb9000000 in
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* instead of 0xe0000000.
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*/
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#define JAZZ_LOCAL_IO_SPACE 0xe0000000
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/*
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* Revision numbers in PICA_ASIC_REVISION
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*
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* 0xf0000000 - Rev1
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* 0xf0000001 - Rev2
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* 0xf0000002 - Rev3
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*/
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#define PICA_ASIC_REVISION 0xe0000008
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/*
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* The segments of the seven segment LED are mapped
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* to the control bits as follows:
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*
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* (7)
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* ---------
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* | |
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* (2) | | (6)
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* | (1) |
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* ---------
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* | |
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* (3) | | (5)
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* | (4) |
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* --------- . (0)
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*/
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#define PICA_LED 0xe000f000
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/*
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* Some characters for the LED control registers
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* The original Mips machines seem to have a LED display
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* with integrated decoder while the Acer machines can
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* control each of the seven segments and the dot independently.
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* It's only a toy, anyway...
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*/
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#define LED_DOT 0x01
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#define LED_SPACE 0x00
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#define LED_0 0xfc
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#define LED_1 0x60
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#define LED_2 0xda
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#define LED_3 0xf2
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#define LED_4 0x66
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#define LED_5 0xb6
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#define LED_6 0xbe
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#define LED_7 0xe0
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#define LED_8 0xfe
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#define LED_9 0xf6
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#define LED_A 0xee
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#define LED_b 0x3e
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#define LED_C 0x9c
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#define LED_d 0x7a
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#define LED_E 0x9e
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#define LED_F 0x8e
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#ifndef __ASSEMBLY__
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static __inline__ void pica_set_led(unsigned int bits)
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{
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volatile unsigned int *led_register = (unsigned int *) PICA_LED;
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*led_register = bits;
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}
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#endif /* !__ASSEMBLY__ */
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/*
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* Base address of the Sonic Ethernet adapter in Jazz machines.
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*/
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#define JAZZ_ETHERNET_BASE 0xe0001000
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/*
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* Base address of the 53C94 SCSI hostadapter in Jazz machines.
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*/
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#define JAZZ_SCSI_BASE 0xe0002000
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/*
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* i8042 keyboard controller for JAZZ and PICA chipsets.
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* This address is just a guess and seems to differ from
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* other mips machines such as RC3xxx...
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*/
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#define JAZZ_KEYBOARD_ADDRESS 0xe0005000
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#define JAZZ_KEYBOARD_DATA 0xe0005000
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#define JAZZ_KEYBOARD_COMMAND 0xe0005001
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned char data;
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unsigned char command;
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} jazz_keyboard_hardware;
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#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
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typedef struct {
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unsigned char pad0[3];
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unsigned char data;
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unsigned char pad1[3];
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unsigned char command;
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} mips_keyboard_hardware;
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/*
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* For now. Needs to be changed for RC3xxx support. See below.
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*/
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#define keyboard_hardware jazz_keyboard_hardware
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#endif /* !__ASSEMBLY__ */
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/*
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* i8042 keyboard controller for most other Mips machines.
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*/
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#define MIPS_KEYBOARD_ADDRESS 0xb9005000
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#define MIPS_KEYBOARD_DATA 0xb9005003
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#define MIPS_KEYBOARD_COMMAND 0xb9005007
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/*
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* Serial and parallel ports (WD 16C552) on the Mips JAZZ
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*/
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#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000
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#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000
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#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000
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/*
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* Dummy Device Address. Used in jazzdma.c
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*/
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#define JAZZ_DUMMY_DEVICE 0xe000d000
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/*
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* JAZZ timer registers and interrupt no.
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* Note that the hardware timer interrupt is actually on
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* cpu level 6, but to keep compatibility with PC stuff
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* it is remapped to vector 0. See arch/mips/kernel/entry.S.
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*/
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#define JAZZ_TIMER_INTERVAL 0xe0000228
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#define JAZZ_TIMER_REGISTER 0xe0000230
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/*
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* DRAM configuration register
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*/
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#ifndef __ASSEMBLY__
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#ifdef __MIPSEL__
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typedef struct {
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unsigned int bank2 : 3;
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unsigned int bank1 : 3;
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unsigned int mem_bus_width : 1;
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unsigned int reserved2 : 1;
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unsigned int page_mode : 1;
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unsigned int reserved1 : 23;
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} dram_configuration;
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#else /* defined (__MIPSEB__) */
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typedef struct {
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unsigned int reserved1 : 23;
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unsigned int page_mode : 1;
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unsigned int reserved2 : 1;
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unsigned int mem_bus_width : 1;
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unsigned int bank1 : 3;
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unsigned int bank2 : 3;
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} dram_configuration;
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#endif
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#endif /* !__ASSEMBLY__ */
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#define PICA_DRAM_CONFIG 0xe00fffe0
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/*
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* JAZZ interrupt control registers
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*/
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#define JAZZ_IO_IRQ_SOURCE 0xe0010000
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#define JAZZ_IO_IRQ_ENABLE 0xe0010002
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/*
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* JAZZ Interrupt Level definitions
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*
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* This is somewhat broken. For reasons which nobody can remember anymore
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* we remap the Jazz interrupts to the usual ISA style interrupt numbers.
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*/
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#define JAZZ_IRQ_START 24
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#define JAZZ_IRQ_END (24 + 9)
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#define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0)
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#define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1)
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#define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2)
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#define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3)
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#define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4)
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#define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5)
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#define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6)
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#define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7)
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#define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8)
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#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9)
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#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
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/*
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* JAZZ DMA Channels
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* Note: Channels 4...7 are not used with respect to the Acer PICA-61
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* chipset which does not provide these DMA channels.
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*/
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#define JAZZ_SCSI_DMA 0 /* SCSI */
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#define JAZZ_FLOPPY_DMA 1 /* FLOPPY */
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#define JAZZ_AUDIOL_DMA 2 /* AUDIO L */
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#define JAZZ_AUDIOR_DMA 3 /* AUDIO R */
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/*
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* JAZZ R4030 MCT_ADR chip (DMA controller)
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* Note: Virtual Addresses !
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*/
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#define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */
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#define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */
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#define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */
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#define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */
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#define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */
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#define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */
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#define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */
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#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */
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#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */
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#define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */
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#define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */
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#define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */
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#define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */
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/*
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* Remote Speed Registers.
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*
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* 0: free, 1: Ethernet, 2: SCSI, 3: Floppy,
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* 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2,
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* 8: parallel, 9: NVRAM, 10: CPU, 11: PROM,
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* 12: reserved, 13: free, 14: 7seg LED, 15: ???
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*/
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#define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */
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/* 0xE0000070,78,80... 0xE00000E8 */
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#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */
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#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */
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#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */
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#define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */
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/*
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* Virtual (E)ISA controller address
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*/
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#define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */
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/*
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* Access the R4030 DMA and I/O Controller
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*/
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#ifndef __ASSEMBLY__
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static inline void r4030_delay(void)
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{
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__asm__ __volatile__(
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".set\tnoreorder\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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".set\treorder");
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}
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static inline unsigned short r4030_read_reg16(unsigned long addr)
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{
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unsigned short ret = *((volatile unsigned short *)addr);
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r4030_delay();
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return ret;
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}
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static inline unsigned int r4030_read_reg32(unsigned long addr)
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{
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unsigned int ret = *((volatile unsigned int *)addr);
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r4030_delay();
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return ret;
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}
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static inline void r4030_write_reg16(unsigned long addr, unsigned val)
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{
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*((volatile unsigned short *)addr) = val;
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r4030_delay();
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}
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static inline void r4030_write_reg32(unsigned long addr, unsigned val)
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{
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*((volatile unsigned int *)addr) = val;
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r4030_delay();
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}
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#endif /* !__ASSEMBLY__ */
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#define JAZZ_FDC_BASE 0xe0003000
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#define JAZZ_RTC_BASE 0xe0004000
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#define JAZZ_PORT_BASE 0xe2000000
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#define JAZZ_EISA_BASE 0xe3000000
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#endif /* __ASM_JAZZ_H */
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