96 lines
2.0 KiB
ArmAsm
96 lines
2.0 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2002, 2007 Maciej W. Rozycki
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* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/loongarch.h>
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#include <asm/regdef.h>
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#include <asm/fpregdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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.align 5
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SYM_FUNC_START(__arch_cpu_idle)
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/* start of rollback region */
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LONG_L t0, tp, TI_FLAGS
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nop
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andi t0, t0, _TIF_NEED_RESCHED
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bnez t0, 1f
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nop
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nop
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nop
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idle 0
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/* end of rollback region */
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1: jr ra
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SYM_FUNC_END(__arch_cpu_idle)
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SYM_FUNC_START(handle_vint)
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BACKUP_T0T1
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SAVE_ALL
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la.abs t1, __arch_cpu_idle
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LONG_L t0, sp, PT_ERA
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/* 32 byte rollback region */
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ori t0, t0, 0x1f
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xori t0, t0, 0x1f
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bne t0, t1, 1f
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LONG_S t0, sp, PT_ERA
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1: move a0, sp
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move a1, sp
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la.abs t0, do_vint
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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SYM_FUNC_END(handle_vint)
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SYM_FUNC_START(except_vec_cex)
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b cache_parity_error
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SYM_FUNC_END(except_vec_cex)
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.macro build_prep_badv
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csrrd t0, LOONGARCH_CSR_BADV
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PTR_S t0, sp, PT_BVADDR
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.endm
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.macro build_prep_fcsr
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movfcsr2gr a1, fcsr0
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.endm
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.macro build_prep_none
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.endm
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.macro BUILD_HANDLER exception handler prep
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.align 5
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SYM_FUNC_START(handle_\exception)
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BACKUP_T0T1
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SAVE_ALL
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build_prep_\prep
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move a0, sp
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la.abs t0, do_\handler
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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SYM_FUNC_END(handle_\exception)
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.endm
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BUILD_HANDLER ade ade badv
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BUILD_HANDLER ale ale badv
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BUILD_HANDLER bp bp none
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BUILD_HANDLER fpe fpe fcsr
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BUILD_HANDLER fpu fpu none
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BUILD_HANDLER lsx lsx none
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BUILD_HANDLER lasx lasx none
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BUILD_HANDLER lbt lbt none
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BUILD_HANDLER ri ri none
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BUILD_HANDLER watch watch none
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BUILD_HANDLER reserved reserved none /* others */
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SYM_FUNC_START(handle_sys)
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la.abs t0, handle_syscall
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jr t0
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SYM_FUNC_END(handle_sys)
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