582 lines
13 KiB
Plaintext
582 lines
13 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Einfochips
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* Copyright 2019 Linaro Ltd.
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*/
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/dts-v1/;
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#include "imx8mq.dtsi"
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/ {
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model = "Einfochips i.MX8MQ Thor96";
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compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq";
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chosen {
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stdout-path = &uart1;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00000000 0x40000000 0 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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user-led1 {
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label = "green:user1";
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gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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user-led2 {
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label = "green:user2";
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gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "none";
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};
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user-led3 {
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label = "green:user3";
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gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc1";
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default-state = "off";
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};
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user-led4 {
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label = "green:user4";
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gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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panic-indicator;
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linux,default-trigger = "none";
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};
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wlan-active-led {
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label = "yellow:wlan";
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gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy0tx";
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default-state = "off";
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};
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bt-active-led {
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label = "blue:bt";
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gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "hci0-power";
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default-state = "off";
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};
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};
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reg_usdhc1_vmmc: reg-usdhc1-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VDD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usdhc1_vqmmc: reg-usdhc1-vqmmc {
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compatible = "regulator-fixed";
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regulator-name = "VCC_1V8_EXT";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_usdhc2_vmmc: reg-usdhc2-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vqmmc: reg-usdhc2-vqmmc {
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compatible = "regulator-fixed";
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regulator-name = "NVCC_SD2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi_reg_on>;
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gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
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};
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};
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/* LS-SPI0 */
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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};
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};
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};
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/* LS-I2C0 */
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x8>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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/* LS-I2C1 */
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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eeprom: eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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};
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};
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/* HS-I2C2 */
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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/* HS-I2C3 */
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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};
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&pgc_gpu {
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power-supply = <&sw1a_reg>;
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};
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&pgc_vpu {
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power-supply = <&sw1c_reg>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi0>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <100000000>;
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reg = <0>;
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};
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};
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/* Debug UART */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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status = "okay";
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};
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/* LS-UART0 */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
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shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_bt_gpios>;
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};
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};
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/* LS-UART1 */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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/* SDIO */
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&usdhc1 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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vmmc-supply = <®_usdhc1_vmmc>;
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vqmmc-supply = <®_usdhc1_vqmmc>;
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mmc-pwrseq = <&sdio_pwrseq>;
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bus-width = <4>;
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non-removable;
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no-sd;
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no-mmc;
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status = "okay";
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brcmf: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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/* uSD */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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vmmc-supply = <®_usdhc2_vmmc>;
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vqmmc-supply = <®_usdhc2_vqmmc>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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no-sdio;
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no-mmc;
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disable-wp;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_bt_gpios: btgpiosgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
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MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19
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MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
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>;
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};
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|
|
pinctrl_ecspi2: ecspi2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16
|
||
|
|
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16
|
||
|
|
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16
|
||
|
|
MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_fec1: fec1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4
|
||
|
|
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24
|
||
|
|
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c
|
||
|
|
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c
|
||
|
|
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c
|
||
|
|
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c
|
||
|
|
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||
|
|
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||
|
|
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||
|
|
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||
|
|
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c
|
||
|
|
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||
|
|
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||
|
|
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c1: i2c1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||
|
|
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c2: i2c2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
|
||
|
|
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c3: i2c3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
|
||
|
|
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_i2c4: i2c4grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
|
||
|
|
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_leds: ledsgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19
|
||
|
|
MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
|
||
|
|
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
|
||
|
|
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
|
||
|
|
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
|
||
|
|
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_qspi0: qspi0grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
|
||
|
|
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
|
||
|
|
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
|
||
|
|
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||
|
|
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||
|
|
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||
|
|
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_reg_usdhc2: regusdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart1: uart1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||
|
|
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart2: uart2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
|
||
|
|
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
|
||
|
|
MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
|
||
|
|
MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_uart3: uart3grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
|
||
|
|
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1: usdhc1grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
||
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
||
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
||
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2: usdhc2grp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
||
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c
|
||
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c
|
||
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc
|
||
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wdog: wdoggrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_wifi_reg_on: wifiregongrp {
|
||
|
|
fsl,pins = <
|
||
|
|
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
|
||
|
|
>;
|
||
|
|
};
|
||
|
|
};
|