81 lines
2.5 KiB
Plaintext
81 lines
2.5 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019-2021 NXP
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* Zhou Guoniu <guoniu.zhou@nxp.com>
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*/
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img_subsys: bus@58000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x58000000 0x0 0x58000000 0x1000000>;
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img_ipg_clk: clock-img-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "img_ipg_clk";
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};
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jpegdec: jpegdec@58400000 {
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reg = <0x58400000 0x00050000>;
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interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-rates = <200000000>, <200000000>;
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power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
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<&pd IMX_SC_R_MJPEG_DEC_S0>,
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<&pd IMX_SC_R_MJPEG_DEC_S1>,
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<&pd IMX_SC_R_MJPEG_DEC_S2>,
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<&pd IMX_SC_R_MJPEG_DEC_S3>;
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};
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jpegenc: jpegenc@58450000 {
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reg = <0x58450000 0x00050000>;
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interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-rates = <200000000>, <200000000>;
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power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
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<&pd IMX_SC_R_MJPEG_ENC_S0>,
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<&pd IMX_SC_R_MJPEG_ENC_S1>,
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<&pd IMX_SC_R_MJPEG_ENC_S2>,
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<&pd IMX_SC_R_MJPEG_ENC_S3>;
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};
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img_jpeg_dec_lpcg: clock-controller@585d0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x585d0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&img_ipg_clk>, <&img_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>,
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<IMX_LPCG_CLK_4>;
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clock-output-names = "img_jpeg_dec_lpcg_clk",
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"img_jpeg_dec_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
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};
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img_jpeg_enc_lpcg: clock-controller@585f0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x585f0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&img_ipg_clk>, <&img_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>,
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<IMX_LPCG_CLK_4>;
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clock-output-names = "img_jpeg_enc_lpcg_clk",
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"img_jpeg_enc_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
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};
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};
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