148 lines
3.1 KiB
C
148 lines
3.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright: (C) 2018 Socionext Inc.
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* Copyright: (C) 2015 Linaro Ltd.
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*/
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#include <linux/cpu_pm.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of_address.h>
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#include <linux/suspend.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/idmap.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#define M10V_MAX_CPU 4
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#define KERNEL_UNBOOT_FLAG 0x12345678
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static void __iomem *m10v_smp_base;
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static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
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{
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unsigned int mpidr, cpu, cluster;
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if (!m10v_smp_base)
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return -ENXIO;
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mpidr = cpu_logical_map(l_cpu);
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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if (cpu >= M10V_MAX_CPU)
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return -EINVAL;
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pr_info("%s: cpu %u l_cpu %u cluster %u\n",
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__func__, cpu, l_cpu, cluster);
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writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
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arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
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return 0;
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}
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static void m10v_smp_init(unsigned int max_cpus)
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{
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unsigned int mpidr, cpu, cluster;
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
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if (!np)
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return;
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m10v_smp_base = of_iomap(np, 0);
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if (!m10v_smp_base)
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return;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
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for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
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writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static void m10v_cpu_die(unsigned int l_cpu)
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{
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gic_cpu_if_down(0);
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v7_exit_coherency_flush(louis);
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wfi();
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}
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static int m10v_cpu_kill(unsigned int l_cpu)
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{
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unsigned int mpidr, cpu;
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mpidr = cpu_logical_map(l_cpu);
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
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return 1;
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}
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#endif
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static struct smp_operations m10v_smp_ops __initdata = {
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.smp_prepare_cpus = m10v_smp_init,
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.smp_boot_secondary = m10v_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = m10v_cpu_die,
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.cpu_kill = m10v_cpu_kill,
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#endif
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};
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CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops);
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static int m10v_pm_valid(suspend_state_t state)
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{
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return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM);
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}
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typedef void (*phys_reset_t)(unsigned long);
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static phys_reset_t phys_reset;
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static int m10v_die(unsigned long arg)
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{
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setup_mm_for_reboot();
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asm("wfi");
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/* Boot just like a secondary */
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phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
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phys_reset(virt_to_phys(cpu_resume));
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return 0;
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}
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static int m10v_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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asm("wfi");
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break;
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case PM_SUSPEND_MEM:
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cpu_pm_enter();
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cpu_suspend(0, m10v_die);
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cpu_pm_exit();
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break;
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}
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return 0;
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}
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static const struct platform_suspend_ops m10v_pm_ops = {
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.valid = m10v_pm_valid,
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.enter = m10v_pm_enter,
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};
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struct clk *m10v_clclk_register(struct device *cpu_dev);
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static int __init m10v_pm_init(void)
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{
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if (of_machine_is_compatible("socionext,milbeaut-evb"))
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suspend_set_ops(&m10v_pm_ops);
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return 0;
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}
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late_initcall(m10v_pm_init);
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