116 lines
2.5 KiB
C
116 lines
2.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*/
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/module.h>
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#include <asm/cacheflush.h>
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#include <asm/cpuidle.h>
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#include <asm/suspend.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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static int imx6sx_idle_finish(unsigned long val)
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{
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/*
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* for Cortex-A7 which has an internal L2
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* cache, need to flush it before powering
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* down ARM platform, since flushing L1 cache
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* here again has very small overhead, compared
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* to adding conditional code for L2 cache type,
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* just call flush_cache_all() is fine.
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*/
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flush_cache_all();
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cpu_do_idle();
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return 0;
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}
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static int imx6sx_enter_wait(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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imx6_set_lpm(WAIT_UNCLOCKED);
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switch (index) {
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case 1:
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cpu_do_idle();
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break;
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case 2:
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imx6_enable_rbc(true);
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imx_gpc_set_arm_power_in_lpm(true);
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imx_set_cpu_jump(0, v7_cpu_resume);
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/* Need to notify there is a cpu pm operation. */
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cpu_pm_enter();
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cpu_cluster_pm_enter();
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cpu_suspend(0, imx6sx_idle_finish);
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cpu_cluster_pm_exit();
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cpu_pm_exit();
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imx_gpc_set_arm_power_in_lpm(false);
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imx6_enable_rbc(false);
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break;
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default:
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break;
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}
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imx6_set_lpm(WAIT_CLOCKED);
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return index;
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}
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static struct cpuidle_driver imx6sx_cpuidle_driver = {
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.name = "imx6sx_cpuidle",
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.owner = THIS_MODULE,
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.states = {
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/* WFI */
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ARM_CPUIDLE_WFI_STATE,
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/* WAIT */
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{
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.exit_latency = 50,
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.target_residency = 75,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx6sx_enter_wait,
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.name = "WAIT",
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.desc = "Clock off",
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},
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/* WAIT + ARM power off */
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{
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/*
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* ARM gating 31us * 5 + RBC clear 65us
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* and some margin for SW execution, here set it
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* to 300us.
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*/
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.exit_latency = 300,
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.target_residency = 500,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx6sx_enter_wait,
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.name = "LOW-POWER-IDLE",
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.desc = "ARM power off",
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},
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},
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.state_count = 3,
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.safe_state_index = 0,
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};
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int __init imx6sx_cpuidle_init(void)
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{
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imx6_set_int_mem_clk_lpm(true);
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imx6_enable_rbc(false);
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imx_gpc_set_l2_mem_power_in_lpm(false);
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/*
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* set ARM power up/down timing to the fastest,
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* sw2iso and sw can be set to one 32K cycle = 31us
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* except for power up sw2iso which need to be
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* larger than LDO ramp up time.
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*/
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imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1);
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imx_gpc_set_arm_power_down_timing(1, 1);
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return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
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}
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