238 lines
7.7 KiB
Plaintext
238 lines
7.7 KiB
Plaintext
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Atmel NAND flash controller bindings
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The NAND flash controller node should be defined under the EBI bus (see
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Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
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One or several NAND devices can be defined under this NAND controller.
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The NAND controller might be connected to an ECC engine.
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* NAND controller bindings:
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Required properties:
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- compatible: should be one of the following
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"atmel,at91rm9200-nand-controller"
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"atmel,at91sam9260-nand-controller"
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"atmel,at91sam9261-nand-controller"
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"atmel,at91sam9g45-nand-controller"
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"atmel,sama5d3-nand-controller"
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"microchip,sam9x60-nand-controller"
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- ranges: empty ranges property to forward EBI ranges definitions.
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- #address-cells: should be set to 2.
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- #size-cells: should be set to 1.
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- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
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controllers.
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- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
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controllers.
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Optional properties:
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- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
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a PMECC engine.
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* NAND device/chip bindings:
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Required properties:
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- reg: describes the CS lines assigned to the NAND device. If the NAND device
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exposes multiple CS lines (multi-dies chips), your reg property will
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contain X tuples of 3 entries.
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1st entry: the CS line this NAND chip is connected to
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2nd entry: the base offset of the memory region assigned to this
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device (always 0)
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3rd entry: the memory region size (always 0x800000)
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Optional properties:
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- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
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- cs-gpios: the GPIO(s) used to control the CS line.
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- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
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- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
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on sama5 SoCs.
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All generic properties described in
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Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
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device node, and NAND partitions should be defined under the NAND node as
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described in Documentation/devicetree/bindings/mtd/partition.txt.
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* ECC engine (PMECC) bindings:
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Required properties:
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- compatible: should be one of the following
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"atmel,at91sam9g45-pmecc"
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"atmel,sama5d4-pmecc"
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"atmel,sama5d2-pmecc"
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"microchip,sam9x60-pmecc"
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- reg: should contain 2 register ranges. The first one is pointing to the PMECC
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block, and the second one to the PMECC_ERRLOC block.
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* SAMA5 NFC I/O bindings:
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SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
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operations. This interface to this logic is placed in a separate I/O range and
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should thus have its own DT node.
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- compatible: should be "atmel,sama5d3-nfc-io", "syscon".
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- reg: should contain the I/O range used to interact with the NFC logic.
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Example:
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nfc_io: nfc-io@70000000 {
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compatible = "atmel,sama5d3-nfc-io", "syscon";
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reg = <0x70000000 0x8000000>;
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};
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pmecc: ecc-engine@ffffc070 {
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compatible = "atmel,at91sam9g45-pmecc";
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reg = <0xffffc070 0x490>,
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<0xffffc500 0x100>;
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};
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ebi: ebi@10000000 {
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compatible = "atmel,sama5d3-ebi";
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#address-cells = <2>;
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#size-cells = <1>;
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atmel,smc = <&hsmc>;
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reg = <0x10000000 0x10000000
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0x40000000 0x30000000>;
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ranges = <0x0 0x0 0x10000000 0x10000000
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0x1 0x0 0x40000000 0x10000000
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0x2 0x0 0x50000000 0x10000000
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0x3 0x0 0x60000000 0x10000000>;
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clocks = <&mck>;
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nand_controller: nand-controller {
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compatible = "atmel,sama5d3-nand-controller";
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atmel,nfc-sram = <&nfc_sram>;
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atmel,nfc-io = <&nfc_io>;
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ecc-engine = <&pmecc>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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nand@3 {
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reg = <0x3 0x0 0x800000>;
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atmel,rb = <0>;
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/*
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* Put generic NAND/MTD properties and
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* subnodes here.
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*/
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};
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};
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};
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-----------------------------------------------------------------------
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Deprecated bindings (should not be used in new device trees):
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Required properties:
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- compatible: The possible values are:
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"atmel,at91rm9200-nand"
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"atmel,sama5d2-nand"
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"atmel,sama5d4-nand"
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- reg : should specify localbus address and size used for the chip,
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and hardware ECC controller if available.
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If the hardware ECC is PMECC, it should contain address and size for
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PMECC and PMECC Error Location controller.
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The PMECC lookup table address and size in ROM is optional. If not
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specified, driver will build it in runtime.
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- atmel,nand-addr-offset : offset for the address latch.
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- atmel,nand-cmd-offset : offset for the command latch.
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- #address-cells, #size-cells : Must be present if the device has sub-nodes
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representing partitions.
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- gpios : specifies the gpio pins to control the NAND device. detect is an
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optional gpio and may be set to 0 if not present.
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Optional properties:
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- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
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- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
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Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
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"soft_bch".
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- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
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capable of BCH encoding and decoding, on devices where it is present.
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- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
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Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
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is "atmel,sama5d2-nand", 32 is also valid.
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- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
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are: 512, 1024.
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- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
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for different sector size. First one is for sector size 512, the next is for
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sector size 1024. If not specified, driver will build the table in runtime.
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- nand-bus-width : 8 or 16 bus width if not present 8
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
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Nand Flash Controller(NFC) is an optional sub-node
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Required properties:
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- compatible : "atmel,sama5d3-nfc".
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- reg : should specify the address and size used for NFC command registers,
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NFC registers and NFC SRAM. NFC SRAM address and size can be absent
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if don't want to use it.
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- clocks: phandle to the peripheral clock
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Optional properties:
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- atmel,write-by-sram: boolean to enable NFC write by SRAM.
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Examples:
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nand0: nand@40000000,0 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x10000000
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0xffffe800 0x200
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>;
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atmel,nand-addr-offset = <21>; /* ale */
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atmel,nand-cmd-offset = <22>; /* cle */
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nand-on-flash-bbt;
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nand-ecc-mode = "soft";
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gpios = <&pioC 13 0 /* rdy */
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&pioC 14 0 /* nce */
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0 /* cd */
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>;
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partition@0 {
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...
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};
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};
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/* for PMECC supported chips */
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = < 0x40000000 0x10000000 /* bus addr & size */
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0xffffe000 0x00000600 /* PMECC addr & size */
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0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
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0x00100000 0x00100000 /* ROM addr & size */
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>;
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atmel,nand-addr-offset = <21>; /* ale */
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atmel,nand-cmd-offset = <22>; /* cle */
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nand-on-flash-bbt;
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nand-ecc-mode = "hw";
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atmel,has-pmecc; /* enable PMECC */
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atmel,pmecc-cap = <2>;
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atmel,pmecc-sector-size = <512>;
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atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
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gpios = <&pioD 5 0 /* rdy */
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&pioD 4 0 /* nce */
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0 /* cd */
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>;
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partition@0 {
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...
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};
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};
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/* for NFC supported chips */
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nand0: nand@40000000 {
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compatible = "atmel,at91rm9200-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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...
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nfc@70000000 {
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compatible = "atmel,sama5d3-nfc";
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&hsmc_clk>
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reg = <
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0x70000000 0x10000000 /* NFC Command Registers */
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0xffffc000 0x00000070 /* NFC HSMC regs */
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0x00200000 0x00100000 /* NFC SRAM banks */
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>;
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};
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};
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