forked from BSB-WS23/mpstubs
92 lines
3.0 KiB
C
92 lines
3.0 KiB
C
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/*! \file
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* \brief \ref Core::MSRs "Identifiers" for \ref Core::MSR "Model-Specific Register"
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*/
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#pragma once
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namespace Core {
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/*! \brief Model-Specific Register Identifiers
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*
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* Selection of useful identifiers.
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*
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* \see [ISDMv4](intel_manual_vol4.pdf)
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*/
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enum MSRs : uint32_t {
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MSR_PLATFORM_INFO = 0xceU, ///< Platform information including bus frequency (Intel)
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MSR_TSC_DEADLINE = 0x6e0U, ///< Register for \ref LAPIC::Timer Deadline mode
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// Fast system calls
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MSR_EFER = 0xC0000080U, ///< Extended Feature Enable Register, \see Core::MSR_EFER
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MSR_STAR = 0xC0000081U, ///< eip (protected mode), ring 0 and 3 segment bases
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MSR_LSTAR = 0xC0000082U, ///< rip (long mode)
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MSR_SFMASK = 0xC0000084U, ///< lower 32 bit: flag mask, if bit is set corresponding rflag is cleared through syscall
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// Core local variables
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MSR_FS_BASE = 0xC0000100U,
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MSR_GS_BASE = 0xC0000101U, ///< Current GS base pointer
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MSR_SHADOW_GS_BASE = 0xC0000102U, ///< Usually called `MSR_KERNEL_GS_BASE` but this is misleading
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};
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/* \brief Important bits in Extended Feature Enable Register (EFER)
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*
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* \see [ISDMv3, 2.2.1 Extended Feature Enable Register](intel_manual_vol3.pdf#page=69)
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* \see [AAPMv2, 3.1.7 Extended Feature Enable Register](amd64_manual_vol2.pdf#page=107)
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*/
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enum MSR_EFER : uintptr_t {
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MSR_EFER_SCE = 1U << 0, ///< System Call Extensions
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MSR_EFER_LME = 1U << 8, ///< Long mode enable
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MSR_EFER_LMA = 1U << 10, ///< Long mode active
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MSR_EFER_NXE = 1U << 11, ///< No-Execute Enable
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MSR_EFER_SVME = 1U << 12, ///< Secure Virtual Machine Enable
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MSR_EFER_LMSLE = 1U << 13, ///< Long Mode Segment Limit Enable
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MSR_EFER_FFXSR = 1U << 14, ///< Fast `FXSAVE`/`FXRSTOR` instruction
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MSR_EFER_TCE = 1U << 15, ///< Translation Cache Extension
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};
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/*! \brief Access to the Model-Specific Register (MSR)
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*
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* \see [ISDMv3, 9.4 Model-Specific Registers (MSRs)](intel_manual_vol3.pdf#page=319)
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* \see [ISDMv4](intel_manual_vol4.pdf)
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* \tparam id ID of the Model-Specific Register to access
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*/
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template<enum MSRs id>
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class MSR {
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/*! \brief Helper to access low and high bits of a 64 bit value
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* \internal
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*/
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union uint64_parts {
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struct {
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uint32_t low;
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uint32_t high;
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} __attribute__((packed));
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uint64_t value;
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explicit uint64_parts(uint64_t value = 0) : value(value) {}
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};
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public:
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/*! \brief Read the value of the current MSR
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*
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* \return Value stored in the MSR
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*
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* \see [ISDMv2, Chapter 4. RDMSR - Read from Model Specific Register](intel_manual_vol2.pdf#page=1186)
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*/
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static inline uint64_t read() {
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uint64_parts p;
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asm volatile ("rdmsr \n\t" : "=a"(p.low), "=d"(p.high) : "c"(id));
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return p.value;
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}
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/*! \brief Write a value into the current MSR
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*
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* \param value Value to write into the MSR
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*
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* \see [ISDMv2, Chapter 5. WRMSR - Write to Model Specific Register](intel_manual_vol2.pdf#page=1912)
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*/
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static inline void write(uint64_t value) {
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uint64_parts p(value);
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asm volatile ("wrmsr \n\t" : : "c"(id), "a"(p.low), "d"(p.high));
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}
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};
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} // namespace Core
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