forked from BSB-WS23/mpstubs
82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
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/*! \file
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* \brief Access to \ref Core::CR "Control Register" of a \ref Core "CPU core"
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*/
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#pragma once
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#include "types.h"
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namespace Core {
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/*! \brief Control Register 0
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*
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* \see [ISDMv3, 2.5 Control Registers](intel_manual_vol3.pdf#page=74)
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*/
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enum CR0 : uintptr_t {
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CR0_PE = 1U << 0, ///< Protected Mode enabled
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CR0_MP = 1U << 1, ///< Monitor co-processor
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CR0_EM = 1U << 2, ///< Emulation (no x87 floating-point unit present)
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CR0_TS = 1U << 3, ///< Task switched
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CR0_ET = 1U << 4, ///< Extension type
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CR0_NE = 1U << 5, ///< Numeric error
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CR0_WP = 1U << 16, ///< Write protect
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CR0_AM = 1U << 18, ///< Alignment mask
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CR0_NW = 1U << 29, ///< Not-write through caching
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CR0_CD = 1U << 30, ///< Cache disable
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CR0_PG = 1U << 31, ///< Paging
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};
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/*! \brief Control Register 4
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*
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* \see [ISDMv3, 2.5 Control Registers](intel_manual_vol3.pdf#page=77)
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*/
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enum CR4 : uintptr_t {
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CR4_VME = 1U << 0, ///< Virtual 8086 Mode Extensions
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CR4_PVI = 1U << 1, ///< Protected-mode Virtual Interrupts
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CR4_TSD = 1U << 2, ///< Time Stamp Disable
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CR4_DE = 1U << 3, ///< Debugging Extensions
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CR4_PSE = 1U << 4, ///< Page Size Extension
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CR4_PAE = 1U << 5, ///< Physical Address Extension
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CR4_MCE = 1U << 6, ///< Machine Check Exception
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CR4_PGE = 1U << 7, ///< Page Global Enabled
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CR4_PCE = 1U << 8, ///< Performance-Monitoring Counter enable
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CR4_OSFXSR = 1U << 9, ///< Operating system support for FXSAVE and FXRSTOR instructions
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CR4_OSXMMEXCPT = 1U << 10, ///< Operating System Support for Unmasked SIMD Floating-Point Exceptions
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CR4_UMIP = 1U << 11, ///< User-Mode Instruction Prevention
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CR4_VMXE = 1U << 13, ///< Virtual Machine Extensions Enable
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CR4_SMXE = 1U << 14, ///< Safer Mode Extensions Enable
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CR4_FSGSBASE = 1U << 16, ///< Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
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CR4_PCIDE = 1U << 17, ///< PCID Enable
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CR4_OSXSAVE = 1U << 18, ///< XSAVE and Processor Extended States Enable
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CR4_SMEP = 1U << 20, ///< Supervisor Mode Execution Protection Enable
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CR4_SMAP = 1U << 21, ///< Supervisor Mode Access Prevention Enable
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CR4_PKE = 1U << 22, ///< Protection Key Enable
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};
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/*! \brief Access to the Control Register
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*
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* \see [ISDMv3, 2.5 Control Registers](intel_manual_vol3.pdf#page=73)
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* \tparam id Control Register to access
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*/
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template<uint8_t id>
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class CR {
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public:
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/*! \brief Read the value of the current Control Register
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*
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* \return Value stored in the CR
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*/
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inline static uintptr_t read(void) {
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uintptr_t val;
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asm volatile("mov %%cr%c1, %0" : "=r"(val) : "n"(id) : "memory");
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return val;
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}
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/*! \brief Write a value into the current Control Register
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*
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* \param value Value to write into the CR
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*/
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inline static void write(uintptr_t value) {
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asm volatile("mov %0, %%cr%c1" : : "r"(value), "n"(id) : "memory");
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}
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};
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} // namespace Core
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