forked from BSB-WS23/mpstubs
113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
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/*! \file
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* \brief Access to internals of a CPU \ref Core
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*/
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/*! \defgroup sync CPU Synchronization
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*
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* The synchronization module houses functions useful for orchestrating multiple processors and their activities.
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* Synchronisation, in this case, means handling the resource contention between multiple participants, running on
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* either the same or different cores.
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*/
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#pragma once
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#include "types.h"
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#include "machine/core_cr.h"
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#include "machine/core_interrupt.h"
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#include "machine/core_msr.h"
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/*! \brief Implements an abstraction for CPU internals.
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*
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* These internals include functions to \ref Core::Interrupt "allow or deny interrupts",
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* access \ref Core::CR "control registers".
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*/
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namespace Core {
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/*! \brief Maximum number of supported CPUs
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*/
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const unsigned MAX = 8;
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/*! \brief Get the ID of the current CPU core
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* using \ref LAPIC::getID() with an internal lookup table.
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*
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* \return ID of current Core (a number between 0 and \ref Core::MAX)
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*/
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unsigned getID();
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/*! \brief Initialize this CPU core
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*
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* Mark this core as *online* and setup the cores \ref LAPIC by assigning it a
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* unique \ref APIC::getLogicalAPICID() "logical APIC ID"
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*
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* \note Should only be called from \ref kernel_init() during startup.
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*/
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void init();
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/*! \brief Deinitialize this CPU core
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*
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* Mark this Core as *offline*
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*
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* \note Should only be called from \ref kernel_init() after returning from `main()` or `main_ap()`.
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*/
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void exit();
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/*! \brief Get number of available CPU cores
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*
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* \return total number of cores
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*/
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unsigned count();
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/*! \brief Get number of successfully started (and currently active) CPU cores
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*
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* \return total number of online cores
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*/
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unsigned countOnline();
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/*! \brief Check if CPU core is currently active
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* \param core_id ID of the CPU core
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* \return `true` if successfully started and is currently active
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*/
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bool isOnline(uint8_t core_id);
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/*! \brief Gives the core a hint that it is executing a spinloop and should sleep "shortly"
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*
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* Improves the over-all performance when executing a spinloop by waiting a short moment reduce
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* the load on the memory.
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*
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* \see [ISDMv2, Chapter 4. PAUSE - Spin Loop Hint](intel_manual_vol2.pdf#page=887)
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*/
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inline void pause() {
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asm volatile("pause\n\t" : : : "memory");
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}
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/*! \brief Halt the CPU core until the next interrupt.
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*
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* Halts the current CPU core such that it will wake up on the next interrupt. Internally, this function first enables
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* the interrupts via `sti` and then halts the core using `hlt`. Halted cores can only be woken by interrupts.
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* The effect of `sti` is delayed by one instruction, making the sequence `sti hlt` atomic (if interrupts were
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* disabled previously).
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*
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* \see [ISDMv2, Chapter 4. STI - Set Interrupt Flag](intel_manual_vol2.pdf#page=1297)
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* \see [ISDMv2, Chapter 3. HLT - Halt](intel_manual_vol2.pdf#page=539)
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*/
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inline void idle() {
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asm volatile("sti\n\t hlt\n\t" : : : "memory");
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}
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/*! \brief Permanently halts the core.
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*
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* Permanently halts the current CPU core. Internally, this function first disables the interrupts via `cli` and
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* then halts the CPU core using `hlt`. As halted CPU cores can only be woken by interrupts, it is guaranteed that
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* this core will be halted until the next reboot. The execution of die never returns.
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* On multicore systems, only the executing CPU core will be halted permanently, other cores will continue execution.
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*
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* \see [ISDMv2, Chapter 3. CLI - Clear Interrupt Flag](intel_manual_vol2.pdf#page=245)
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* \see [ISDMv2, Chapter 3. HLT - Halt](intel_manual_vol2.pdf#page=539)
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*/
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[[noreturn]] inline void die() {
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while (true) {
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asm volatile("cli\n\t hlt\n\t" : : : "memory");
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}
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}
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} // namespace Core
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