86 lines
1.9 KiB
ArmAsm
86 lines
1.9 KiB
ArmAsm
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
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v_interp_p1_f32 v5, v1, attr0.x
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// CHECK: [0x01,0x00,0x14,0xd4]
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v_interp_p1_f32 v255, v1, attr0.x
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// CHECK: [0x01,0x00,0xfc,0xd7]
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v_interp_p1_f32 v5, v255, attr0.x
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// CHECK: [0xff,0x00,0x14,0xd4]
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v_interp_p1_f32 v5, v1, attr1.x
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// CHECK: [0x01,0x04,0x14,0xd4]
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v_interp_p1_f32 v5, v1, attr31.x
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// CHECK: [0x01,0x7c,0x14,0xd4]
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v_interp_p1_f32 v5, v1, attr32.x
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// CHECK: [0x01,0x80,0x14,0xd4]
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v_interp_p1_f32 v5, v1, attr0.y
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// CHECK: [0x01,0x01,0x14,0xd4]
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v_interp_p1_f32 v5, v1, attr0.z
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// CHECK: [0x01,0x02,0x14,0xd4]
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v_interp_p1_f32 v5, v1, attr0.w
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// CHECK: [0x01,0x03,0x14,0xd4]
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v_interp_p2_f32 v5, v1, attr0.x
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// CHECK: [0x01,0x00,0x15,0xd4]
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v_interp_p2_f32 v255, v1, attr0.x
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// CHECK: [0x01,0x00,0xfd,0xd7]
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v_interp_p2_f32 v5, v255, attr0.x
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// CHECK: [0xff,0x00,0x15,0xd4]
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v_interp_p2_f32 v5, v1, attr1.x
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// CHECK: [0x01,0x04,0x15,0xd4]
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v_interp_p2_f32 v5, v1, attr31.x
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// CHECK: [0x01,0x7c,0x15,0xd4]
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v_interp_p2_f32 v5, v1, attr32.x
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// CHECK: [0x01,0x80,0x15,0xd4]
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v_interp_p2_f32 v5, v1, attr0.y
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// CHECK: [0x01,0x01,0x15,0xd4]
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v_interp_p2_f32 v5, v1, attr0.z
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// CHECK: [0x01,0x02,0x15,0xd4]
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v_interp_p2_f32 v5, v1, attr0.w
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// CHECK: [0x01,0x03,0x15,0xd4]
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v_interp_mov_f32 v5, p10, attr0.x
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// CHECK: [0x00,0x00,0x16,0xd4]
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v_interp_mov_f32 v255, p10, attr0.x
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// CHECK: [0x00,0x00,0xfe,0xd7]
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v_interp_mov_f32 v5, p20, attr0.x
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// CHECK: [0x01,0x00,0x16,0xd4]
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v_interp_mov_f32 v5, p0, attr0.x
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// CHECK: [0x02,0x00,0x16,0xd4]
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v_interp_mov_f32 v5, p10, attr1.x
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// CHECK: [0x00,0x04,0x16,0xd4]
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v_interp_mov_f32 v5, p10, attr31.x
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// CHECK: [0x00,0x7c,0x16,0xd4]
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v_interp_mov_f32 v5, p10, attr32.x
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// CHECK: [0x00,0x80,0x16,0xd4]
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v_interp_mov_f32 v5, p10, attr0.y
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// CHECK: [0x00,0x01,0x16,0xd4]
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v_interp_mov_f32 v5, p10, attr0.z
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// CHECK: [0x00,0x02,0x16,0xd4]
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v_interp_mov_f32 v5, p10, attr0.w
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// CHECK: [0x00,0x03,0x16,0xd4]
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