337 lines
10 KiB
ArmAsm
337 lines
10 KiB
ArmAsm
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// ---------------------------------------------------------------------------//
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// Test 64-bit form (x0) and its aliases
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// ---------------------------------------------------------------------------//
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uqdech x0
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// CHECK-INST: uqdech x0
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// CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
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uqdech x0, all
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// CHECK-INST: uqdech x0
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// CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
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uqdech x0, all, mul #1
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// CHECK-INST: uqdech x0
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// CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
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uqdech x0, all, mul #16
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// CHECK-INST: uqdech x0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xff,0x7f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 7f 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test 32-bit form (w0) and its aliases
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// ---------------------------------------------------------------------------//
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uqdech w0
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// CHECK-INST: uqdech w0
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// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
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uqdech w0, all
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// CHECK-INST: uqdech w0
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// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
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uqdech w0, all, mul #1
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// CHECK-INST: uqdech w0
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// CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
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uqdech w0, all, mul #16
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// CHECK-INST: uqdech w0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 ff 6f 04 <unknown>
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uqdech w0, pow2
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// CHECK-INST: uqdech w0, pow2
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// CHECK-ENCODING: [0x00,0xfc,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fc 60 04 <unknown>
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uqdech w0, pow2, mul #16
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// CHECK-INST: uqdech w0, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fc 6f 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test vector form and aliases.
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// ---------------------------------------------------------------------------//
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uqdech z0.h
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// CHECK-INST: uqdech z0.h
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// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
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uqdech z0.h, all
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// CHECK-INST: uqdech z0.h
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// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
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uqdech z0.h, all, mul #1
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// CHECK-INST: uqdech z0.h
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// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
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uqdech z0.h, all, mul #16
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// CHECK-INST: uqdech z0.h, all, mul #16
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// CHECK-ENCODING: [0xe0,0xcf,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 cf 6f 04 <unknown>
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uqdech z0.h, pow2
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// CHECK-INST: uqdech z0.h, pow2
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// CHECK-ENCODING: [0x00,0xcc,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 cc 60 04 <unknown>
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uqdech z0.h, pow2, mul #16
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// CHECK-INST: uqdech z0.h, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xcc,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 cc 6f 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test all patterns for 64-bit form
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// ---------------------------------------------------------------------------//
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uqdech x0, pow2
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// CHECK-INST: uqdech x0, pow2
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// CHECK-ENCODING: [0x00,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fc 70 04 <unknown>
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uqdech x0, vl1
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// CHECK-INST: uqdech x0, vl1
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// CHECK-ENCODING: [0x20,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 fc 70 04 <unknown>
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uqdech x0, vl2
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// CHECK-INST: uqdech x0, vl2
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// CHECK-ENCODING: [0x40,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 fc 70 04 <unknown>
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uqdech x0, vl3
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// CHECK-INST: uqdech x0, vl3
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// CHECK-ENCODING: [0x60,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 fc 70 04 <unknown>
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uqdech x0, vl4
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// CHECK-INST: uqdech x0, vl4
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// CHECK-ENCODING: [0x80,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 fc 70 04 <unknown>
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uqdech x0, vl5
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// CHECK-INST: uqdech x0, vl5
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// CHECK-ENCODING: [0xa0,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 fc 70 04 <unknown>
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uqdech x0, vl6
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// CHECK-INST: uqdech x0, vl6
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// CHECK-ENCODING: [0xc0,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 fc 70 04 <unknown>
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uqdech x0, vl7
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// CHECK-INST: uqdech x0, vl7
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// CHECK-ENCODING: [0xe0,0xfc,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fc 70 04 <unknown>
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uqdech x0, vl8
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// CHECK-INST: uqdech x0, vl8
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// CHECK-ENCODING: [0x00,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fd 70 04 <unknown>
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uqdech x0, vl16
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// CHECK-INST: uqdech x0, vl16
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// CHECK-ENCODING: [0x20,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 fd 70 04 <unknown>
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uqdech x0, vl32
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// CHECK-INST: uqdech x0, vl32
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// CHECK-ENCODING: [0x40,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 fd 70 04 <unknown>
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uqdech x0, vl64
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// CHECK-INST: uqdech x0, vl64
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// CHECK-ENCODING: [0x60,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 fd 70 04 <unknown>
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uqdech x0, vl128
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// CHECK-INST: uqdech x0, vl128
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// CHECK-ENCODING: [0x80,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 fd 70 04 <unknown>
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uqdech x0, vl256
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// CHECK-INST: uqdech x0, vl256
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// CHECK-ENCODING: [0xa0,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 fd 70 04 <unknown>
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uqdech x0, #14
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// CHECK-INST: uqdech x0, #14
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// CHECK-ENCODING: [0xc0,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 fd 70 04 <unknown>
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uqdech x0, #15
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// CHECK-INST: uqdech x0, #15
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// CHECK-ENCODING: [0xe0,0xfd,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fd 70 04 <unknown>
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uqdech x0, #16
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// CHECK-INST: uqdech x0, #16
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// CHECK-ENCODING: [0x00,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 fe 70 04 <unknown>
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uqdech x0, #17
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// CHECK-INST: uqdech x0, #17
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// CHECK-ENCODING: [0x20,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 fe 70 04 <unknown>
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uqdech x0, #18
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// CHECK-INST: uqdech x0, #18
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// CHECK-ENCODING: [0x40,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 fe 70 04 <unknown>
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uqdech x0, #19
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// CHECK-INST: uqdech x0, #19
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// CHECK-ENCODING: [0x60,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 fe 70 04 <unknown>
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uqdech x0, #20
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// CHECK-INST: uqdech x0, #20
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// CHECK-ENCODING: [0x80,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 fe 70 04 <unknown>
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uqdech x0, #21
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// CHECK-INST: uqdech x0, #21
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// CHECK-ENCODING: [0xa0,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 fe 70 04 <unknown>
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uqdech x0, #22
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// CHECK-INST: uqdech x0, #22
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// CHECK-ENCODING: [0xc0,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 fe 70 04 <unknown>
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uqdech x0, #23
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// CHECK-INST: uqdech x0, #23
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// CHECK-ENCODING: [0xe0,0xfe,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 fe 70 04 <unknown>
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uqdech x0, #24
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// CHECK-INST: uqdech x0, #24
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// CHECK-ENCODING: [0x00,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 ff 70 04 <unknown>
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uqdech x0, #25
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// CHECK-INST: uqdech x0, #25
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// CHECK-ENCODING: [0x20,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 ff 70 04 <unknown>
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uqdech x0, #26
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// CHECK-INST: uqdech x0, #26
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// CHECK-ENCODING: [0x40,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 ff 70 04 <unknown>
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uqdech x0, #27
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// CHECK-INST: uqdech x0, #27
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// CHECK-ENCODING: [0x60,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 ff 70 04 <unknown>
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uqdech x0, #28
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// CHECK-INST: uqdech x0, #28
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// CHECK-ENCODING: [0x80,0xff,0x70,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 ff 70 04 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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uqdech z0.h
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// CHECK-INST: uqdech z0.h
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// CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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uqdech z0.h, pow2, mul #16
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// CHECK-INST: uqdech z0.h, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xcc,0x6f,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 cc 6f 04 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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uqdech z0.h, pow2
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// CHECK-INST: uqdech z0.h, pow2
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// CHECK-ENCODING: [0x00,0xcc,0x60,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 cc 60 04 <unknown>
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