98 lines
3.6 KiB
ArmAsm
98 lines
3.6 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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stnt1h z23.h, p0, [x13, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: stnt1h z23.h, p0, [x13, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z29.h, p0, [x3, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: stnt1h z29.h, p0, [x3, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid source type.
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stnt1h z0.b, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: stnt1h z0.b, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z0.s, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: stnt1h z0.s, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z0.d, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: stnt1h z0.d, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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stnt1h z27.h, p8, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: stnt1h z27.h, p8, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z0.h, p0/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: stnt1h z0.h, p0/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z0.h, p0/m, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: stnt1h z0.h, p0/m, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z0.h, p7.b, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: stnt1h z0.h, p7.b, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h z0.h, p7.q, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: stnt1h z0.h, p7.q, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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stnt1h { }, p0, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: stnt1h { }, p0, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h { z1.h, z2.h }, p0, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: stnt1h { z1.h, z2.h }, p0, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stnt1h { v0.2d }, p0, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: stnt1h { v0.2d }, p0, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.h, p0/z, z7.h
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stnt1h { z0.h }, p0, [x0, x0, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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stnt1h { z0.h }, p0, [x0, x0, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: stnt1h { z0.h }, p0, [x0, x0, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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