123 lines
5.5 KiB
ArmAsm
123 lines
5.5 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-32, 28].
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st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-36, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-36, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #32, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #32, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Immediate not a multiple of four.
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st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-7, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: st4w {z12.s, z13.s, z14.s, z15.s}, p4, [x12, #-7, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28].
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// CHECK-NEXT: st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w {z2.s, z3.s, z4.s, z5.s}, p7.b, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p7.b, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w {z2.s, z3.s, z4.s, z5.s}, p7.q, [x15, #10, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p7.q, [x15, #10, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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st4w { }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: st4w { }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z2.s, z3.s, z4.s }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s, z4.s }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z21.s, p5/z, z28.s
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st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z21, z28
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st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st4w { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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