195 lines
7.6 KiB
ArmAsm
195 lines
7.6 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// invalid/missing predicate operation specifier
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prfw p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch hint expected
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// CHECK-NEXT: prfw p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #16, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch operand out of range, [0,15] expected
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// CHECK-NEXT: prfw #16, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw plil1keep, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: prefetch hint expected
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// CHECK-NEXT: prfw plil1keep, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #pldl1keep, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate value expected for prefetch operand
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// CHECK-NEXT: prfw #pldl1keep, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// invalid scalar + scalar addressing modes
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prfw #0, p0, [x0, #-33, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
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// CHECK-NEXT: prfw #0, p0, [x0, #-33, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, #32, mul vl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
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// CHECK-NEXT: prfw #0, p0, [x0, #32, mul vl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: prfw #0, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, x0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: prfw #0, p0, [x0, x0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, x0, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: prfw #0, p0, [x0, x0, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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prfw #0, p0, [x0, z0.h]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: prfw #0, p0, [x0, z0.h]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
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// CHECK-NEXT: prfw #0, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
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// CHECK-NEXT: prfw #0, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, z0.s, uxtw #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
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// CHECK-NEXT: prfw #0, p0, [x0, z0.s, uxtw #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, z0.s, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
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// CHECK-NEXT: prfw #0, p0, [x0, z0.s, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, z0.d, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
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// CHECK-NEXT: prfw #0, p0, [x0, z0.d, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [x0, z0.d, sxtw #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
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// CHECK-NEXT: prfw #0, p0, [x0, z0.d, sxtw #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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prfw #0, p0, [z0.s, #-4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.s, #-4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.s, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.s, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.s, #125]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.s, #125]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.s, #128]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.s, #128]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.s, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.s, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.d, #-4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.d, #-4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.d, #125]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.d, #125]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.d, #128]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.d, #128]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p0, [z0.d, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: prfw #0, p0, [z0.d, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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prfw #0, p8, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: prfw #0, p8, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p7.b, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: prfw #0, p7.b, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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prfw #0, p7.q, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: prfw #0, p7.q, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z8.d, p3/z, z15.d
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prfw #7, p3, [x13, z8.d, uxtw #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z8, z15
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prfw #7, p3, [x13, z8.d, uxtw #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: prfw #7, p3, [x13, z8.d, uxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z21.d, p5/z, z28.d
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prfw pldl3strm, p5, [x10, z21.d, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z21, z28
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prfw pldl3strm, p5, [x10, z21.d, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: prfw pldl3strm, p5, [x10, z21.d, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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